arm: dts: rockchip: Sync rv1126 dts from linux 6.8-rc1
Sync linux dts files for rv1126 boards from linux v6.8-rc1 tag. Includes
the newly added dts for Sonoff iHost.
Signed-off-by: Tim Lunn <tim@feathertop.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/arch/arm/dts/rv1126.dtsi b/arch/arm/dts/rv1126.dtsi
index 1cb4314..bb603ca 100644
--- a/arch/arm/dts/rv1126.dtsi
+++ b/arch/arm/dts/rv1126.dtsi
@@ -21,6 +21,13 @@
aliases {
i2c0 = &i2c0;
+ i2c2 = &i2c2;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
};
cpus {
@@ -83,6 +90,11 @@
clock-frequency = <24000000>;
};
+ display_subsystem {
+ compatible = "rockchip,display-subsystem";
+ ports = <&vop_out>;
+ };
+
xin24m: oscillator {
compatible = "fixed-clock";
clock-frequency = <24000000>;
@@ -125,6 +137,26 @@
reg = <0xfe86c000 0x20>;
};
+ qos_iep: qos@fe8a0000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe8a0000 0x20>;
+ };
+
+ qos_rga_rd: qos@fe8a0080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe8a0080 0x20>;
+ };
+
+ qos_rga_wr: qos@fe8a0100 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe8a0100 0x20>;
+ };
+
+ qos_vop: qos@fe8a0180 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe8a0180 0x20>;
+ };
+
gic: interrupt-controller@feff0000 {
compatible = "arm,gic-400";
interrupt-controller;
@@ -170,6 +202,25 @@
pm_qos = <&qos_sdio>;
#power-domain-cells = <0>;
};
+
+ power-domain@RV1126_PD_VO {
+ reg = <RV1126_PD_VO>;
+ clocks = <&cru ACLK_RGA>,
+ <&cru HCLK_RGA>,
+ <&cru CLK_RGA_CORE>,
+ <&cru ACLK_VOP>,
+ <&cru HCLK_VOP>,
+ <&cru DCLK_VOP>,
+ <&cru PCLK_DSIHOST>,
+ <&cru ACLK_IEP>,
+ <&cru HCLK_IEP>,
+ <&cru CLK_IEP_CORE>;
+ pm_qos = <&qos_rga_rd>,
+ <&qos_rga_wr>,
+ <&qos_vop>,
+ <&qos_iep>;
+ #power-domain-cells = <0>;
+ };
};
};
@@ -187,6 +238,20 @@
status = "disabled";
};
+ i2c2: i2c@ff400000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff400000 0x1000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C2>, <&pmucru PCLK_I2C2>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart1: serial@ff410000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff410000 0x100>;
@@ -203,6 +268,17 @@
status = "disabled";
};
+ pwm2: pwm@ff430020 {
+ compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff430020 0x10>;
+ clock-names = "pwm", "pclk";
+ clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm2m0_pins>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
pmucru: clock-controller@ff480000 {
compatible = "rockchip,rv1126-pmucru";
reg = <0xff480000 0x1000>;
@@ -232,6 +308,17 @@
clock-names = "apb_pclk";
};
+ pwm11: pwm@ff550030 {
+ compatible = "rockchip,rv1126-pwm", "rockchip,rk3328-pwm";
+ reg = <0xff550030 0x10>;
+ clock-names = "pwm", "pclk";
+ clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
+ pinctrl-0 = <&pwm11m0_pins>;
+ pinctrl-names = "default";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
uart0: serial@ff560000 {
compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
reg = <0xff560000 0x100>;
@@ -332,6 +419,92 @@
clock-names = "pclk", "timer";
};
+ vop: vop@ffb00000 {
+ compatible = "rockchip,rv1126-vop";
+ reg = <0xffb00000 0x200>, <0xffb00a00 0x400>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
+ clocks = <&cru ACLK_VOP>, <&cru DCLK_VOP>, <&cru HCLK_VOP>;
+ reset-names = "axi", "ahb", "dclk";
+ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
+ iommus = <&vop_mmu>;
+ power-domains = <&power RV1126_PD_VO>;
+ status = "disabled";
+
+ vop_out: port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ vop_out_rgb: endpoint@0 {
+ reg = <0>;
+ };
+
+ vop_out_dsi: endpoint@1 {
+ reg = <1>;
+ };
+ };
+ };
+
+ vop_mmu: iommu@ffb00f00 {
+ compatible = "rockchip,iommu";
+ reg = <0xffb00f00 0x100>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "aclk", "iface";
+ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+ #iommu-cells = <0>;
+ power-domains = <&power RV1126_PD_VO>;
+ status = "disabled";
+ };
+
+ gmac: ethernet@ffc40000 {
+ compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a";
+ reg = <0xffc40000 0x4000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq", "eth_wake_irq";
+ rockchip,grf = <&grf>;
+ clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
+ <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>,
+ <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
+ <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>;
+ clock-names = "stmmaceth", "mac_clk_rx",
+ "mac_clk_tx", "clk_mac_ref",
+ "aclk_mac", "pclk_mac",
+ "clk_mac_speed", "ptp_ref";
+ resets = <&cru SRST_GMAC_A>;
+ reset-names = "stmmaceth";
+
+ snps,mixed-burst;
+ snps,tso;
+
+ snps,axi-config = <&stmmac_axi_setup>;
+ snps,mtl-rx-config = <&mtl_rx_setup>;
+ snps,mtl-tx-config = <&mtl_tx_setup>;
+ status = "disabled";
+
+ mdio: mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <0x1>;
+ #size-cells = <0x0>;
+ };
+
+ stmmac_axi_setup: stmmac-axi-config {
+ snps,wr_osr_lmt = <4>;
+ snps,rd_osr_lmt = <8>;
+ snps,blen = <0 0 0 0 16 8 4>;
+ };
+
+ mtl_rx_setup: rx-queues-config {
+ snps,rx-queues-to-use = <1>;
+ queue0 {};
+ };
+
+ mtl_tx_setup: tx-queues-config {
+ snps,tx-queues-to-use = <1>;
+ queue0 {};
+ };
+ };
+
emmc: mmc@ffc50000 {
compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
reg = <0xffc50000 0x4000>;
@@ -370,6 +543,18 @@
status = "disabled";
};
+ sfc: spi@ffc90000 {
+ compatible = "rockchip,sfc";
+ reg = <0xffc90000 0x4000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ assigned-clocks = <&cru SCLK_SFC>;
+ assigned-clock-rates = <80000000>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
pinctrl: pinctrl {
compatible = "rockchip,rv1126-pinctrl";
rockchip,grf = <&grf>;