clk: mediatek: add configurable pcw_chg_reg/ibits/fmin to mtk_pll
Add configurable pcw_chg_reg/ibits/fmin to mtk_pll to support mt8512
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 450de98..3345591 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -95,11 +95,13 @@
{
int pcwbits = pll->pcwbits;
int pcwfbits;
+ int ibits;
u64 vco;
u8 c = 0;
/* The fractional part of the PLL divider. */
- pcwfbits = pcwbits > INTEGER_BITS ? pcwbits - INTEGER_BITS : 0;
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ pcwfbits = pcwbits > ibits ? pcwbits - ibits : 0;
vco = (u64)fin * pcw;
@@ -124,7 +126,7 @@
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- u32 val;
+ u32 val, chg;
/* set postdiv */
val = readl(priv->base + pll->pd_reg);
@@ -140,11 +142,16 @@
/* set pcw */
val &= ~GENMASK(pll->pcw_shift + pll->pcwbits - 1, pll->pcw_shift);
val |= pcw << pll->pcw_shift;
- val &= ~CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
- val |= CON1_PCW_CHG;
- writel(val, priv->base + pll->pcw_reg);
+ if (pll->pcw_chg_reg) {
+ chg = readl(priv->base + pll->pcw_chg_reg);
+ chg |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ writel(chg, priv->base + pll->pcw_chg_reg);
+ } else {
+ val |= CON1_PCW_CHG;
+ writel(val, priv->base + pll->pcw_reg);
+ }
udelay(20);
}
@@ -161,8 +168,9 @@
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_pll_data *pll = &priv->tree->plls[clk->id];
- unsigned long fmin = 1000 * MHZ;
+ unsigned long fmin = pll->fmin ? pll->fmin : 1000 * MHZ;
u64 _pcw;
+ int ibits;
u32 val;
if (freq > pll->fmax)
@@ -175,7 +183,8 @@
}
/* _pcw = freq * postdiv / xtal_rate * 2^pcwfbits */
- _pcw = ((u64)freq << val) << (pll->pcwbits - INTEGER_BITS);
+ ibits = pll->pcwibits ? pll->pcwibits : INTEGER_BITS;
+ _pcw = ((u64)freq << val) << (pll->pcwbits - ibits);
do_div(_pcw, priv->tree->xtal2_rate);
*pcw = (u32)_pcw;