commit 07a5cb9d3b9bf9bca9ca207b82f92eac73cbdda8
author Marek Behún <marek.behun@nic.cz> Tue Jul 23 16:49:32 2019 +0200
committer Jagan Teki <jagan@amarulasolutions.com> Mon Sep 16 08:09:22 2019 +0530
tree 3f2db1a85c43f293b5cd76444118a12943bbcbc2
parent 23b93e33adde0a8313388eda7c78d1d0786e3c92

spi: mvebu_a3700_spi: Fix clock prescale computation

The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong.
Set the upper bound of the value to 0x1f with the min macro.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

drivers/spi/mvebu_a3700_spi.c

diff --git a/drivers/spi/mvebu_a3700_spi.c b/drivers/spi/mvebu_a3700_spi.c
index feeafdc..99ad505 100644
--- a/drivers/spi/mvebu_a3700_spi.c
+++ b/drivers/spi/mvebu_a3700_spi.c
@@ -181,10 +181,9 @@
 	data = readl(&reg->cfg);
 
 	prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
-	if (prescale > 0x1f)
-		prescale = 0x1f;
-	else if (prescale > 0xf)
+	if (prescale > 0xf)
 		prescale = 0x10 + (prescale + 1) / 2;
+	prescale = min(prescale, 0x1fu);
 
 	data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
 	data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;