| commit | 054dfd9b9d9fedac87bffdbde72683e8e678eecc | [log] [tgz] |
|---|---|---|
| author | York Sun <yorksun@freescale.com> | Mon Mar 25 07:33:19 2013 +0000 |
| committer | Andy Fleming <afleming@freescale.com> | Tue May 14 16:00:27 2013 -0500 |
| tree | 4bc2a6de51e662a1234814a7a1ce6622aaa1f7d0 | |
| parent | f9772444a0fe326f7c986884df6c0b39d19fef06 [diff] |
powerpc/t4240qds: Update DDR timing table Update the timing table to support more rank density, based on the theory that similar density DIMMs have similar clock adjust and write level start timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>