commit 0caac5f4155a1db6c5ce921c7f9294b6b46e7744
author Lei Wen <[leiwen@marvell.com]> Tue Nov 01 16:25:56 2011 +0530
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Thu Nov 03 22:56:22 2011 +0100
tree c8749f7c0bb033051d9ea07f2d950fd527023098
parent f779d739d67653c0d77f50cb18c315b2d39de075

pantheon: define CONFIG_SYS_CACHELINE_SIZE

By default, on Pantheon SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>

arch/arm/include/asm/arch-pantheon/config.h

diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
index d10583d..e4fce7d 100644
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -28,6 +28,8 @@
 #include <asm/arch/pantheon.h>
 
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
+/* default Dcache Line length for pantheon */
+#define CONFIG_SYS_CACHELINE_SIZE	32
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
 #define CONFIG_SYS_HZ_CLOCK	(3250000)	/* Timer Freq. 3.25MHZ */