clk: exynos: Move pll code into clk-exynos7420
PLL utilities code is only used by clk-exynos7420 driver at the moment.
Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
clocks implementation, which is coming in the next patches.
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Chanho Park <chanho61.park@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index 7d869eb..9caa932 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -10,8 +10,15 @@
#include <errno.h>
#include <clk-uclass.h>
#include <asm/io.h>
+#include <div64.h>
#include <dt-bindings/clock/exynos7420-clk.h>
-#include "clk-pll.h"
+
+#define PLL145X_MDIV_SHIFT 16
+#define PLL145X_MDIV_MASK 0x3ff
+#define PLL145X_PDIV_SHIFT 8
+#define PLL145X_PDIV_MASK 0x3f
+#define PLL145X_SDIV_SHIFT 0
+#define PLL145X_SDIV_MASK 0x7
#define DIVIDER(reg, shift, mask) \
(((readl(reg) >> shift) & mask) + 1)
@@ -64,6 +71,22 @@
unsigned long sclk_uart2;
};
+static unsigned long pll145x_get_rate(unsigned int *con1,
+ unsigned long fin_freq)
+{
+ unsigned long pll_con1 = readl(con1);
+ unsigned long mdiv, sdiv, pdiv;
+ u64 fvco = fin_freq;
+
+ mdiv = (pll_con1 >> PLL145X_MDIV_SHIFT) & PLL145X_MDIV_MASK;
+ pdiv = (pll_con1 >> PLL145X_PDIV_SHIFT) & PLL145X_PDIV_MASK;
+ sdiv = (pll_con1 >> PLL145X_SDIV_SHIFT) & PLL145X_SDIV_MASK;
+
+ fvco *= mdiv;
+ do_div(fvco, (pdiv << sdiv));
+ return (unsigned long)fvco;
+}
+
static ulong exynos7420_topc_get_rate(struct clk *clk)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);