riscv: Add a SYSCON driver for Andestech's PLIC
The Platform-Level Interrupt Controller (PLIC)
block holds memory-mapped claim and pending registers
associated with software interrupt. It is required
for handling IPI.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
index 35dbf64..1bf554b 100644
--- a/arch/riscv/lib/Makefile
+++ b/arch/riscv/lib/Makefile
@@ -11,6 +11,7 @@
obj-y += cache.o
obj-$(CONFIG_RISCV_RDTIME) += rdtime.o
obj-$(CONFIG_SIFIVE_CLINT) += sifive_clint.o
+obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
obj-y += interrupts.o
obj-y += reset.o
obj-$(CONFIG_SBI_IPI) += sbi_ipi.o