commit 0ebf40417df79ca0b73fa3fca0f6d13f47c5b530
author Michal Simek <michal.simek@xilinx.com> Mon Oct 05 12:49:48 2015 +0200
committer Michal Simek <michal.simek@xilinx.com> Thu Nov 19 13:09:21 2015 +0100
tree d8716cd27c4eee460b7df0fc1f82fafc36f7aa36
parent 97a51a036336c82d206e35b1235c679241db72a7

net: zynq: Fix clearing statistic

Previous loop was completely bogus. Iterration should go just over
statistic counters.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

drivers/net/zynq_gem.c

diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index fae61a0..41ac829 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -129,7 +129,8 @@
 	u32 laddr[4][LADDR_HIGH + 1]; /* 0x8c - Specific1 addr low/high reg */
 	u32 match[4]; /* 0xa8 - Type ID1 Match reg */
 	u32 reserved6[18];
-	u32 stat[44]; /* 0x100 - Octects transmitted Low reg - stat start */
+#define STAT_SIZE	44
+	u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */
 };
 
 /* BD descriptors */
@@ -301,8 +302,6 @@
 	u32 i;
 	unsigned long clk_rate = 0;
 	struct phy_device *phydev;
-	const u32 stat_size = (sizeof(struct zynq_gem_regs) -
-				offsetof(struct zynq_gem_regs, stat)) / 4;
 	struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
 	struct zynq_gem_priv *priv = dev->priv;
 	const u32 supported = SUPPORTED_10baseT_Half |
@@ -330,7 +329,7 @@
 		writel(0x0, &regs->hashh);
 
 		/* Clear all counters */
-		for (i = 0; i <= stat_size; i++)
+		for (i = 0; i < STAT_SIZE; i++)
 			readl(&regs->stat[i]);
 
 		/* Setup RxBD space */