net: sunxi_emac: Add CLK support
Add CLk support for sunxi_emac to enable AHB_EMAC clock
via CLK framework.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c
index 8dbd3c5..9a5f7fd 100644
--- a/drivers/net/sunxi_emac.c
+++ b/drivers/net/sunxi_emac.c
@@ -6,6 +6,7 @@
*/
#include <common.h>
+#include <clk.h>
#include <dm.h>
#include <linux/err.h>
#include <malloc.h>
@@ -157,6 +158,7 @@
struct emac_eth_dev {
struct emac_regs *regs;
+ struct clk clk;
struct mii_dev *bus;
struct phy_device *phydev;
int link_printed;
@@ -500,14 +502,12 @@
return 0;
}
-static void sunxi_emac_board_setup(struct emac_eth_dev *priv)
+static int sunxi_emac_board_setup(struct emac_eth_dev *priv)
{
- struct sunxi_ccm_reg *const ccm =
- (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
struct sunxi_sramc_regs *sram =
(struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE;
struct emac_regs *regs = priv->regs;
- int pin;
+ int pin, ret;
/* Map SRAM to EMAC */
setbits_le32(&sram->ctrl1, 0x5 << 2);
@@ -517,10 +517,16 @@
sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC);
/* Set up clock gating */
- setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_EMAC);
+ ret = clk_enable(&priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable emac clock\n");
+ return ret;
+ }
/* Set MII clock */
clrsetbits_le32(®s->mac_mcfg, 0xf << 2, 0xd << 2);
+
+ return 0;
}
static int sunxi_emac_eth_start(struct udevice *dev)
@@ -557,9 +563,19 @@
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct emac_eth_dev *priv = dev_get_priv(dev);
+ int ret;
priv->regs = (struct emac_regs *)pdata->iobase;
- sunxi_emac_board_setup(priv);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret) {
+ dev_err(dev, "failed to get emac clock\n");
+ return ret;
+ }
+
+ ret = sunxi_emac_board_setup(priv);
+ if (ret)
+ return ret;
return sunxi_emac_init_phy(priv, dev);
}