imx8ulp: clock: Support to enable/disable the ADC1 clock
This patch implements enable_adc1_clk() to enable or disable the ADC1
clock on i.MX8ULP.
Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/arch/arm/mach-imx/imx8ulp/pcc.c b/arch/arm/mach-imx/imx8ulp/pcc.c
index 6145b3e..7909d77 100644
--- a/arch/arm/mach-imx/imx8ulp/pcc.c
+++ b/arch/arm/mach-imx/imx8ulp/pcc.c
@@ -15,6 +15,21 @@
#define cgc_clk_TYPES 2
#define cgc_clk_NUM 8
+static enum cgc_clk pcc1_clksrc[][8] = {
+ {
+ },
+ {
+ DUMMY0_CLK,
+ LPOSC,
+ SOSC_DIV2,
+ FRO_DIV2,
+ CM33_BUSCLK,
+ PLL1_VCO_DIV,
+ PLL0_PFD2_DIV,
+ PLL0_PFD1_DIV,
+ }
+};
+
static enum cgc_clk pcc3_clksrc[][8] = {
{
},
@@ -75,6 +90,11 @@
}
};
+static struct pcc_entry pcc1_arrays[] = {
+ {PCC1_RBASE, ADC1_PCC1_SLOT, CLKSRC_PER_BUS, PCC_NO_DIV, PCC_HAS_RST_B},
+ {}
+};
+
static struct pcc_entry pcc3_arrays[] = {
{PCC3_RBASE, DMA1_MP_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
{PCC3_RBASE, DMA1_CH0_PCC3_SLOT, CLKSRC_NO_PCS, PCC_NO_DIV, PCC_NO_RST_B},
@@ -228,6 +248,10 @@
int index = 0;
switch (pcc_controller) {
+ case 1:
+ pcc_array = pcc1_arrays;
+ *out = &pcc1_arrays[0];
+ break;
case 3:
pcc_array = pcc3_arrays;
*out = &pcc3_arrays[0];
@@ -310,7 +334,9 @@
return -EPERM;
}
- if (pcc_controller == 3)
+ if (pcc_controller == 1)
+ cgc_clk_array = pcc1_clksrc[clksrc_type];
+ else if (pcc_controller == 3)
cgc_clk_array = pcc3_clksrc[clksrc_type];
else if (pcc_controller == 4)
cgc_clk_array = pcc4_clksrc[clksrc_type];