xilinx: Disable ARCH_FIXUP_FDT_MEMORY
Based on DT spec you can have one memory node which multiple ranges or
multiple nodes.
fdt_fixup_memory_banks() is not implemented in a correct way when multiple
memory nodes are present because all ranges are put it to the first memory
node found. And next memory nodes are kept in DT which ends up in the same
range specification in the same DT.
Here is what it is happening.
Origin DT.
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
memory@800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
After fdt_fixup_memory_banks()
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
memory@800000000 {
device_type = "memory";
reg = <0x8 0x00000000 0x0 0x80000000>;
};
As is visible memory@0 node got second range but there is still
memory@800000000 node present and 2G range is listed twice.
The solution can't be that second node is removed because it can be
referenced already that's why it is better for us to disable this option
for now.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/configs/xilinx_zynq_virt_defconfig b/configs/xilinx_zynq_virt_defconfig
index b4c7f11..573a10f 100644
--- a/configs/xilinx_zynq_virt_defconfig
+++ b/configs/xilinx_zynq_virt_defconfig
@@ -23,6 +23,7 @@
CONFIG_SPL_LOAD_FIT_ADDRESS=0x10000000
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
CONFIG_USE_PREBOOT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_FPGA=y