mpc83xx: fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx
pcie controller is connected with switch or we use both of the two
pcie controller.
Signed-off-by: Leo Liu <liucai.lfn@gmail.com>
fix codingstyle and compiler warning: 'pcie_priv' defined but not used
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c
index 46a706d..52d4461 100644
--- a/arch/powerpc/cpu/mpc83xx/pcie.c
+++ b/arch/powerpc/cpu/mpc83xx/pcie.c
@@ -48,11 +48,26 @@
#ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES
+/* private structure for mpc83xx pcie hose */
+static struct mpc83xx_pcie_priv {
+ u8 index;
+} pcie_priv[PCIE_MAX_BUSES] = {
+ {
+ /* pcie controller 1 */
+ .index = 0,
+ },
+ {
+ /* pcie controller 2 */
+ .index = 1,
+ },
+};
+
static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev)
{
int bus = PCI_BUS(dev) - hose->first_busno;
immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- pex83xx_t *pex = &immr->pciexp[bus];
+ struct mpc83xx_pcie_priv *pcie_priv = hose->priv_data;
+ pex83xx_t *pex = &immr->pciexp[pcie_priv->index];
struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0];
u8 devfn = PCI_DEV(dev) << 3 | PCI_FUNC(dev);
u32 dev_base = bus << 24 | devfn << 16;
@@ -142,6 +157,8 @@
hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base;
+ hose->priv_data = &pcie_priv[bus];
+
pci_set_ops(hose,
pcie_read_config_byte,
pcie_read_config_word,
diff --git a/include/pci.h b/include/pci.h
index e80b6bd..c6b264b 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -420,6 +420,8 @@
/* Used by ppc405 autoconfig*/
struct pci_region *pci_fb;
int current_busno;
+
+ void *priv_data;
};
extern __inline__ void pci_set_ops(struct pci_controller *hose,