clk: convert API to match reset/mailbox style
The following changes are made to the clock API:
* The concept of "clocks" and "peripheral clocks" are unified; each clock
provider now implements a single set of clocks. This provides a simpler
conceptual interface to clients, and better aligns with device tree
clock bindings.
* Clocks are now identified with a single "struct clk", rather than
requiring clients to store the clock provider device and clock identity
values separately. For simple clock consumers, this isolates clients
from internal details of the clock API.
* clk.h is split so it only contains the client/consumer API, whereas
clk-uclass.h contains the provider API. This aligns with the recently
added reset and mailbox APIs.
* clk_ops .of_xlate(), .request(), and .free() are added so providers
can customize these operations if needed. This also aligns with the
recently added reset and mailbox APIs.
* clk_disable() is added.
* All users of the current clock APIs are updated.
* Sandbox clock tests are updated to exercise clock lookup via DT, and
clock enable/disable.
* rkclk_get_clk() is removed and replaced with standard APIs.
Buildman shows no clock-related errors for any board for which buildman
can download a toolchain.
test/py passes for sandbox (which invokes the dm clk test amongst
others).
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
diff --git a/drivers/clk/exynos/clk-exynos7420.c b/drivers/clk/exynos/clk-exynos7420.c
index bf5d0e6..1f017a3 100644
--- a/drivers/clk/exynos/clk-exynos7420.c
+++ b/drivers/clk/exynos/clk-exynos7420.c
@@ -9,7 +9,7 @@
#include <common.h>
#include <dm.h>
#include <errno.h>
-#include <clk.h>
+#include <clk-uclass.h>
#include <asm/io.h>
#include <dt-bindings/clock/exynos7420-clk.h>
#include "clk-pll.h"
@@ -67,11 +67,11 @@
unsigned long sclk_uart2;
};
-static ulong exynos7420_topc_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_topc_get_rate(struct clk *clk)
{
- struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
+ struct exynos7420_clk_topc_priv *priv = dev_get_priv(clk->dev);
- switch (periph) {
+ switch (clk->id) {
case DOUT_SCLK_BUS0_PLL:
case SCLK_BUS0_PLL_A:
case SCLK_BUS0_PLL_B:
@@ -86,14 +86,14 @@
}
static struct clk_ops exynos7420_clk_topc_ops = {
- .get_periph_rate = exynos7420_topc_get_periph_rate,
+ .get_rate = exynos7420_topc_get_rate,
};
static int exynos7420_clk_topc_probe(struct udevice *dev)
{
struct exynos7420_clk_topc_priv *priv = dev_get_priv(dev);
struct exynos7420_clk_cmu_topc *topc;
- struct udevice *clk_dev;
+ struct clk in_clk;
unsigned long rate;
fdt_addr_t base;
int ret;
@@ -105,9 +105,9 @@
topc = (struct exynos7420_clk_cmu_topc *)base;
priv->topc = topc;
- ret = clk_get_by_index(dev, 0, &clk_dev);
+ ret = clk_get_by_index(dev, 0, &in_clk);
if (ret >= 0)
- priv->fin_freq = clk_get_rate(clk_dev);
+ priv->fin_freq = clk_get_rate(&in_clk);
rate = pll145x_get_rate(&topc->bus0_pll_con[0], priv->fin_freq);
if (readl(&topc->mux_sel[1]) & (1 << 16))
@@ -122,12 +122,12 @@
return 0;
}
-static ulong exynos7420_top0_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_top0_get_rate(struct clk *clk)
{
- struct exynos7420_clk_top0_priv *priv = dev_get_priv(dev);
+ struct exynos7420_clk_top0_priv *priv = dev_get_priv(clk->dev);
struct exynos7420_clk_cmu_top0 *top0 = priv->top0;
- switch (periph) {
+ switch (clk->id) {
case CLK_SCLK_UART2:
return priv->mout_top0_bus0_pll_half /
DIVIDER(&top0->div_peric[3], 8, 0xf);
@@ -137,14 +137,14 @@
}
static struct clk_ops exynos7420_clk_top0_ops = {
- .get_periph_rate = exynos7420_top0_get_periph_rate,
+ .get_rate = exynos7420_top0_get_rate,
};
static int exynos7420_clk_top0_probe(struct udevice *dev)
{
struct exynos7420_clk_top0_priv *priv;
struct exynos7420_clk_cmu_top0 *top0;
- struct udevice *clk_dev;
+ struct clk in_clk;
fdt_addr_t base;
int ret;
@@ -159,10 +159,10 @@
top0 = (struct exynos7420_clk_cmu_top0 *)base;
priv->top0 = top0;
- ret = clk_get_by_index(dev, 1, &clk_dev);
+ ret = clk_get_by_index(dev, 1, &in_clk);
if (ret >= 0) {
priv->mout_top0_bus0_pll_half =
- clk_get_periph_rate(clk_dev, ret);
+ clk_get_rate(&in_clk);
if (readl(&top0->mux_sel[1]) & (1 << 16))
priv->mout_top0_bus0_pll_half >>= 1;
}
@@ -170,18 +170,18 @@
return 0;
}
-static ulong exynos7420_peric1_get_periph_rate(struct udevice *dev, int periph)
+static ulong exynos7420_peric1_get_rate(struct clk *clk)
{
- struct udevice *clk_dev;
+ struct clk in_clk;
unsigned int ret;
unsigned long freq = 0;
- switch (periph) {
+ switch (clk->id) {
case SCLK_UART2:
- ret = clk_get_by_index(dev, 3, &clk_dev);
+ ret = clk_get_by_index(clk->dev, 3, &in_clk);
if (ret < 0)
return ret;
- freq = clk_get_periph_rate(clk_dev, ret);
+ freq = clk_get_rate(&in_clk);
break;
}
@@ -189,7 +189,7 @@
}
static struct clk_ops exynos7420_clk_peric1_ops = {
- .get_periph_rate = exynos7420_peric1_get_periph_rate,
+ .get_rate = exynos7420_peric1_get_rate,
};
static const struct udevice_id exynos7420_clk_topc_compat[] = {