ARM: dts: stm32: Sync DT with v4.20 kernel for stm32h7
Synchronize stm32h7 device tree with kernel v4.20.
U-boot DT files and pinctrl bindings are updated,
useless nodes are removed and gpio compatible added.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
diff --git a/arch/arm/dts/stm32h7-u-boot.dtsi b/arch/arm/dts/stm32h7-u-boot.dtsi
index 6e5b805..99fa0e6 100644
--- a/arch/arm/dts/stm32h7-u-boot.dtsi
+++ b/arch/arm/dts/stm32h7-u-boot.dtsi
@@ -43,10 +43,21 @@
* second bank is bank@1
*/
bank1: bank@1 {
- st,sdram-control = /bits/ 8 <NO_COL_9 NO_ROW_12 MWIDTH_32 BANKS_4
- CAS_2 SDCLK_3 RD_BURST_EN RD_PIPE_DL_0>;
- st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_1 TRAS_1 TRC_6 TRP_2
- TWR_1 TRCD_1>;
+ st,sdram-control = /bits/ 8 <NO_COL_9
+ NO_ROW_12
+ MWIDTH_32
+ BANKS_4
+ CAS_2
+ SDCLK_3
+ RD_BURST_EN
+ RD_PIPE_DL_0>;
+ st,sdram-timing = /bits/ 8 <TMRD_1
+ TXSR_1
+ TRAS_1
+ TRC_6
+ TRP_2
+ TWR_1
+ TRCD_1>;
st,sdram-refcount = <1539>;
};
};
@@ -81,134 +92,137 @@
u-boot,dm-pre-reloc;
};
-&clk_hsi {
- u-boot,dm-pre-reloc;
-};
-
-&clk_csi {
- u-boot,dm-pre-reloc;
-};
-
&gpioa {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpiob {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpioc {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpiod {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpioe {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpiof {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpiog {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpioh {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpioi {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpioj {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&gpiok {
u-boot,dm-pre-reloc;
+ compatible = "st,stm32-gpio";
};
&pinctrl {
fmc_pins: fmc@0 {
- pins {
- pinmux = <STM32H7_PD0_FUNC_FMC_D2_FMC_DA2>,
- <STM32H7_PD1_FUNC_FMC_D3_FMC_DA3>,
- <STM32H7_PD8_FUNC_FMC_D13_FMC_DA13>,
- <STM32H7_PD9_FUNC_FMC_D14_FMC_DA14>,
- <STM32H7_PD10_FUNC_FMC_D15_FMC_DA15>,
- <STM32H7_PD14_FUNC_FMC_D0_FMC_DA0>,
- <STM32H7_PD15_FUNC_FMC_D1_FMC_DA1>,
+ pins {
+ pinmux = <STM32_PINMUX('D', 0, AF12)>,
+ <STM32_PINMUX('D', 1, AF12)>,
+ <STM32_PINMUX('D', 8, AF12)>,
+ <STM32_PINMUX('D', 9, AF12)>,
+ <STM32_PINMUX('D',10, AF12)>,
+ <STM32_PINMUX('D',14, AF12)>,
+ <STM32_PINMUX('D',15, AF12)>,
- <STM32H7_PE0_FUNC_FMC_NBL0>,
- <STM32H7_PE1_FUNC_FMC_NBL1>,
- <STM32H7_PE7_FUNC_FMC_D4_FMC_DA4>,
- <STM32H7_PE8_FUNC_FMC_D5_FMC_DA5>,
- <STM32H7_PE9_FUNC_FMC_D6_FMC_DA6>,
- <STM32H7_PE10_FUNC_FMC_D7_FMC_DA7>,
- <STM32H7_PE11_FUNC_FMC_D8_FMC_DA8>,
- <STM32H7_PE12_FUNC_FMC_D9_FMC_DA9>,
- <STM32H7_PE13_FUNC_FMC_D10_FMC_DA10>,
- <STM32H7_PE14_FUNC_FMC_D11_FMC_DA11>,
- <STM32H7_PE15_FUNC_FMC_D12_FMC_DA12>,
+ <STM32_PINMUX('E', 0, AF12)>,
+ <STM32_PINMUX('E', 1, AF12)>,
+ <STM32_PINMUX('E', 7, AF12)>,
+ <STM32_PINMUX('E', 8, AF12)>,
+ <STM32_PINMUX('E', 9, AF12)>,
+ <STM32_PINMUX('E',10, AF12)>,
+ <STM32_PINMUX('E',11, AF12)>,
+ <STM32_PINMUX('E',12, AF12)>,
+ <STM32_PINMUX('E',13, AF12)>,
+ <STM32_PINMUX('E',14, AF12)>,
+ <STM32_PINMUX('E',15, AF12)>,
- <STM32H7_PF0_FUNC_FMC_A0>,
- <STM32H7_PF1_FUNC_FMC_A1>,
- <STM32H7_PF2_FUNC_FMC_A2>,
- <STM32H7_PF3_FUNC_FMC_A3>,
- <STM32H7_PF4_FUNC_FMC_A4>,
- <STM32H7_PF5_FUNC_FMC_A5>,
- <STM32H7_PF11_FUNC_FMC_SDNRAS>,
- <STM32H7_PF12_FUNC_FMC_A6>,
- <STM32H7_PF13_FUNC_FMC_A7>,
- <STM32H7_PF14_FUNC_FMC_A8>,
- <STM32H7_PF15_FUNC_FMC_A9>,
+ <STM32_PINMUX('F', 0, AF12)>,
+ <STM32_PINMUX('F', 1, AF12)>,
+ <STM32_PINMUX('F', 2, AF12)>,
+ <STM32_PINMUX('F', 3, AF12)>,
+ <STM32_PINMUX('F', 4, AF12)>,
+ <STM32_PINMUX('F', 5, AF12)>,
+ <STM32_PINMUX('F',11, AF12)>,
+ <STM32_PINMUX('F',12, AF12)>,
+ <STM32_PINMUX('F',13, AF12)>,
+ <STM32_PINMUX('F',14, AF12)>,
+ <STM32_PINMUX('F',15, AF12)>,
- <STM32H7_PG0_FUNC_FMC_A10>,
- <STM32H7_PG1_FUNC_FMC_A11>,
- <STM32H7_PG2_FUNC_FMC_A12>,
- <STM32H7_PG4_FUNC_FMC_A14_FMC_BA0>,
- <STM32H7_PG5_FUNC_FMC_A15_FMC_BA1>,
- <STM32H7_PG8_FUNC_FMC_SDCLK>,
- <STM32H7_PG15_FUNC_FMC_SDNCAS>,
+ <STM32_PINMUX('G', 0, AF12)>,
+ <STM32_PINMUX('G', 1, AF12)>,
+ <STM32_PINMUX('G', 2, AF12)>,
+ <STM32_PINMUX('G', 4, AF12)>,
+ <STM32_PINMUX('G', 5, AF12)>,
+ <STM32_PINMUX('G', 8, AF12)>,
+ <STM32_PINMUX('G',15, AF12)>,
- <STM32H7_PH5_FUNC_FMC_SDNWE>,
- <STM32H7_PH6_FUNC_FMC_SDNE1>,
- <STM32H7_PH7_FUNC_FMC_SDCKE1>,
- <STM32H7_PH8_FUNC_FMC_D16>,
- <STM32H7_PH9_FUNC_FMC_D17>,
- <STM32H7_PH10_FUNC_FMC_D18>,
- <STM32H7_PH11_FUNC_FMC_D19>,
- <STM32H7_PH12_FUNC_FMC_D20>,
- <STM32H7_PH13_FUNC_FMC_D21>,
- <STM32H7_PH14_FUNC_FMC_D22>,
- <STM32H7_PH15_FUNC_FMC_D23>,
+ <STM32_PINMUX('H', 5, AF12)>,
+ <STM32_PINMUX('H', 6, AF12)>,
+ <STM32_PINMUX('H', 7, AF12)>,
+ <STM32_PINMUX('H', 8, AF12)>,
+ <STM32_PINMUX('H', 9, AF12)>,
+ <STM32_PINMUX('H',10, AF12)>,
+ <STM32_PINMUX('H',11, AF12)>,
+ <STM32_PINMUX('H',12, AF12)>,
+ <STM32_PINMUX('H',13, AF12)>,
+ <STM32_PINMUX('H',14, AF12)>,
+ <STM32_PINMUX('H',15, AF12)>,
- <STM32H7_PI0_FUNC_FMC_D24>,
- <STM32H7_PI1_FUNC_FMC_D25>,
- <STM32H7_PI2_FUNC_FMC_D26>,
- <STM32H7_PI3_FUNC_FMC_D27>,
- <STM32H7_PI4_FUNC_FMC_NBL2>,
- <STM32H7_PI5_FUNC_FMC_NBL3>,
- <STM32H7_PI6_FUNC_FMC_D28>,
- <STM32H7_PI7_FUNC_FMC_D29>,
- <STM32H7_PI9_FUNC_FMC_D30>,
- <STM32H7_PI10_FUNC_FMC_D31>;
+ <STM32_PINMUX('I', 0, AF12)>,
+ <STM32_PINMUX('I', 1, AF12)>,
+ <STM32_PINMUX('I', 2, AF12)>,
+ <STM32_PINMUX('I', 3, AF12)>,
+ <STM32_PINMUX('I', 4, AF12)>,
+ <STM32_PINMUX('I', 5, AF12)>,
+ <STM32_PINMUX('I', 6, AF12)>,
+ <STM32_PINMUX('I', 7, AF12)>,
+ <STM32_PINMUX('I', 9, AF12)>,
+ <STM32_PINMUX('I',10, AF12)>;
- slew-rate = <3>;
+ slew-rate = <3>;
};
};
pinctrl_sdmmc1_level_shifter: sdmmc0_ls@0 {
pins {
- pinmux = <STM32H7_PB8_FUNC_SDMMC1_CKIN>,
- <STM32H7_PB9_FUNC_SDMMC1_CDIR>,
- <STM32H7_PC6_FUNC_SDMMC1_D0DIR>,
- <STM32H7_PC7_FUNC_SDMMC1_D123DIR>;
+ pinmux = <STM32_PINMUX('B', 8, AF7)>,
+ <STM32_PINMUX('B', 9, AF7)>,
+ <STM32_PINMUX('C', 6, AF8)>,
+ <STM32_PINMUX('C', 7, AF8)>;
drive-push-pull;
slew-rate = <3>;
};
@@ -216,12 +230,12 @@
sdmmc1_pins: sdmmc@0 {
pins {
- pinmux = <STM32H7_PC8_FUNC_SDMMC1_D0>,
- <STM32H7_PC9_FUNC_SDMMC1_D1>,
- <STM32H7_PC10_FUNC_SDMMC1_D2>,
- <STM32H7_PC11_FUNC_SDMMC1_D3>,
- <STM32H7_PC12_FUNC_SDMMC1_CK>,
- <STM32H7_PD2_FUNC_SDMMC1_CMD>;
+ pinmux = <STM32_PINMUX('C', 8, AF12)>,
+ <STM32_PINMUX('C', 9, AF12)>,
+ <STM32_PINMUX('C',10, AF12)>,
+ <STM32_PINMUX('C',11, AF12)>,
+ <STM32_PINMUX('C',12, AF12)>,
+ <STM32_PINMUX('D', 2, AF12)>;
slew-rate = <3>;
drive-push-pull;
diff --git a/arch/arm/dts/stm32h743-pinctrl.dtsi b/arch/arm/dts/stm32h743-pinctrl.dtsi
index 85b96be..c823541 100644
--- a/arch/arm/dts/stm32h743-pinctrl.dtsi
+++ b/arch/arm/dts/stm32h743-pinctrl.dtsi
@@ -40,7 +40,7 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include <dt-bindings/pinctrl/stm32h7-pinfunc.h>
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
/ {
soc {
@@ -49,132 +49,175 @@
#size-cells = <1>;
compatible = "st,stm32h743-pinctrl";
ranges = <0 0x58020000 0x3000>;
+ interrupt-parent = <&exti>;
+ st,syscfg = <&syscfg 0x8>;
pins-are-numbered;
gpioa: gpio@58020000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x0 0x400>;
clocks = <&rcc GPIOA_CK>;
st,bank-name = "GPIOA";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiob: gpio@58020400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x400 0x400>;
clocks = <&rcc GPIOB_CK>;
st,bank-name = "GPIOB";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioc: gpio@58020800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x800 0x400>;
clocks = <&rcc GPIOC_CK>;
st,bank-name = "GPIOC";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiod: gpio@58020c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0xc00 0x400>;
clocks = <&rcc GPIOD_CK>;
st,bank-name = "GPIOD";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioe: gpio@58021000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1000 0x400>;
clocks = <&rcc GPIOE_CK>;
st,bank-name = "GPIOE";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiof: gpio@58021400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1400 0x400>;
clocks = <&rcc GPIOF_CK>;
st,bank-name = "GPIOF";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiog: gpio@58021800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1800 0x400>;
clocks = <&rcc GPIOG_CK>;
st,bank-name = "GPIOG";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioh: gpio@58021c00 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x1c00 0x400>;
clocks = <&rcc GPIOH_CK>;
st,bank-name = "GPIOH";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioi: gpio@58022000 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2000 0x400>;
clocks = <&rcc GPIOI_CK>;
st,bank-name = "GPIOI";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpioj: gpio@58022400 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2400 0x400>;
clocks = <&rcc GPIOJ_CK>;
st,bank-name = "GPIOJ";
+ interrupt-controller;
+ #interrupt-cells = <2>;
};
gpiok: gpio@58022800 {
gpio-controller;
#gpio-cells = <2>;
- compatible = "st,stm32-gpio";
reg = <0x2800 0x400>;
clocks = <&rcc GPIOK_CK>;
st,bank-name = "GPIOK";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ i2c1_pins_a: i2c1@0 {
+ pins {
+ pinmux = <STM32_PINMUX('B', 6, AF4)>, /* I2C1_SCL */
+ <STM32_PINMUX('B', 7, AF4)>; /* I2C1_SDA */
+ bias-disable;
+ drive-open-drain;
+ slew-rate = <0>;
+ };
};
usart1_pins: usart1@0 {
pins1 {
- pinmux = <STM32H7_PB14_FUNC_USART1_TX>;
+ pinmux = <STM32_PINMUX('B', 14, AF4)>; /* USART1_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32H7_PB15_FUNC_USART1_RX>;
+ pinmux = <STM32_PINMUX('B', 15, AF4)>; /* USART1_RX */
bias-disable;
};
};
usart2_pins: usart2@0 {
pins1 {
- pinmux = <STM32H7_PD5_FUNC_USART2_TX>;
+ pinmux = <STM32_PINMUX('D', 5, AF7)>; /* USART2_TX */
bias-disable;
drive-push-pull;
slew-rate = <0>;
};
pins2 {
- pinmux = <STM32H7_PD6_FUNC_USART2_RX>;
+ pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */
bias-disable;
};
};
+
+ usbotg_hs_pins_a: usbotg-hs@0 {
+ pins {
+ pinmux = <STM32_PINMUX('H', 4, AF10)>, /* ULPI_NXT */
+ <STM32_PINMUX('I', 11, AF10)>, /* ULPI_DIR> */
+ <STM32_PINMUX('C', 0, AF10)>, /* ULPI_STP> */
+ <STM32_PINMUX('A', 5, AF10)>, /* ULPI_CK> */
+ <STM32_PINMUX('A', 3, AF10)>, /* ULPI_D0> */
+ <STM32_PINMUX('B', 0, AF10)>, /* ULPI_D1> */
+ <STM32_PINMUX('B', 1, AF10)>, /* ULPI_D2> */
+ <STM32_PINMUX('B', 10, AF10)>, /* ULPI_D3> */
+ <STM32_PINMUX('B', 11, AF10)>, /* ULPI_D4> */
+ <STM32_PINMUX('B', 12, AF10)>, /* ULPI_D5> */
+ <STM32_PINMUX('B', 13, AF10)>, /* ULPI_D6> */
+ <STM32_PINMUX('B', 5, AF10)>; /* ULPI_D7> */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
};
};
};
diff --git a/arch/arm/dts/stm32h743.dtsi b/arch/arm/dts/stm32h743.dtsi
index 23e185c..cbdd69ca 100644
--- a/arch/arm/dts/stm32h743.dtsi
+++ b/arch/arm/dts/stm32h743.dtsi
@@ -44,13 +44,14 @@
#include "armv7-m.dtsi"
#include <dt-bindings/clock/stm32h7-clks.h>
#include <dt-bindings/mfd/stm32h7-rcc.h>
+#include <dt-bindings/interrupt-controller/irq.h>
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <25000000>;
+ clock-frequency = <0>;
};
clk_lse: clk-lse {
@@ -67,31 +68,6 @@
};
soc {
- rcc: rcc@58024400 {
- #clock-cells = <1>;
- #reset-cells = <1>;
- compatible = "st,stm32h743-rcc", "st,stm32-rcc";
- reg = <0x58024400 0x400>;
- clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>, <&clk_hsi>, <&clk_csi>;
- st,syscfg = <&pwrcfg>;
- };
-
- usart1: serial@40011000 {
- compatible = "st,stm32h7-uart";
- reg = <0x40011000 0x400>;
- interrupts = <37>;
- status = "disabled";
- clocks = <&rcc USART1_CK>;
- };
-
- usart2: serial@40004400 {
- compatible = "st,stm32h7-uart";
- reg = <0x40004400 0x400>;
- interrupts = <38>;
- status = "disabled";
- clocks = <&rcc USART2_CK>;
- };
-
timer5: timer@40000c00 {
compatible = "st,stm32-timer";
reg = <0x40000c00 0x400>;
@@ -99,21 +75,441 @@
clocks = <&rcc TIM5_CK>;
};
+ lptimer1: timer@40002400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x40002400 0x400>;
+ clocks = <&rcc LPTIM1_CK>;
+ clock-names = "mux";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@0 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <0>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+ };
+
+ spi2: spi@40003800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40003800 0x400>;
+ interrupts = <36>;
+ clocks = <&rcc SPI2_CK>;
+ status = "disabled";
+
+ };
+
+ spi3: spi@40003c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40003c00 0x400>;
+ interrupts = <51>;
+ clocks = <&rcc SPI3_CK>;
+ status = "disabled";
+ };
+
+ usart2: serial@40004400 {
+ compatible = "st,stm32f7-uart";
+ reg = <0x40004400 0x400>;
+ interrupts = <38>;
+ status = "disabled";
+ clocks = <&rcc USART2_CK>;
+ };
+
+ i2c1: i2c@40005400 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005400 0x400>;
+ interrupts = <31>,
+ <32>;
+ resets = <&rcc STM32H7_APB1L_RESET(I2C1)>;
+ clocks = <&rcc I2C1_CK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@40005800 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005800 0x400>;
+ interrupts = <33>,
+ <34>;
+ resets = <&rcc STM32H7_APB1L_RESET(I2C2)>;
+ clocks = <&rcc I2C2_CK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@40005C00 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x40005C00 0x400>;
+ interrupts = <72>,
+ <73>;
+ resets = <&rcc STM32H7_APB1L_RESET(I2C3)>;
+ clocks = <&rcc I2C3_CK>;
+ status = "disabled";
+ };
+
+ dac: dac@40007400 {
+ compatible = "st,stm32h7-dac-core";
+ reg = <0x40007400 0x400>;
+ clocks = <&rcc DAC12_CK>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ dac1: dac@1 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <1>;
+ status = "disabled";
+ };
+
+ dac2: dac@2 {
+ compatible = "st,stm32-dac";
+ #io-channels-cells = <1>;
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ usart1: serial@40011000 {
+ compatible = "st,stm32f7-uart";
+ reg = <0x40011000 0x400>;
+ interrupts = <37>;
+ status = "disabled";
+ clocks = <&rcc USART1_CK>;
+ };
+
+ spi1: spi@40013000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40013000 0x400>;
+ interrupts = <35>;
+ clocks = <&rcc SPI1_CK>;
+ status = "disabled";
+ };
+
+ spi4: spi@40013400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40013400 0x400>;
+ interrupts = <84>;
+ clocks = <&rcc SPI4_CK>;
+ status = "disabled";
+ };
+
+ spi5: spi@40015000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x40015000 0x400>;
+ interrupts = <85>;
+ clocks = <&rcc SPI5_CK>;
+ status = "disabled";
+ };
+
+ dma1: dma@40020000 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020000 0x400>;
+ interrupts = <11>,
+ <12>,
+ <13>,
+ <14>,
+ <15>,
+ <16>,
+ <17>,
+ <47>;
+ clocks = <&rcc DMA1_CK>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ status = "disabled";
+ };
+
+ dma2: dma@40020400 {
+ compatible = "st,stm32-dma";
+ reg = <0x40020400 0x400>;
+ interrupts = <56>,
+ <57>,
+ <58>,
+ <59>,
+ <60>,
+ <68>,
+ <69>,
+ <70>;
+ clocks = <&rcc DMA2_CK>;
+ #dma-cells = <4>;
+ st,mem2mem;
+ dma-requests = <8>;
+ status = "disabled";
+ };
+
+ dmamux1: dma-router@40020800 {
+ compatible = "st,stm32h7-dmamux";
+ reg = <0x40020800 0x1c>;
+ #dma-cells = <3>;
+ dma-channels = <16>;
+ dma-requests = <128>;
+ dma-masters = <&dma1 &dma2>;
+ clocks = <&rcc DMA1_CK>;
+ };
+
+ adc_12: adc@40022000 {
+ compatible = "st,stm32h7-adc-core";
+ reg = <0x40022000 0x400>;
+ interrupts = <18>;
+ clocks = <&rcc ADC12_CK>;
+ clock-names = "bus";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+
+ adc1: adc@0 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_12>;
+ interrupts = <0>;
+ status = "disabled";
+ };
+
+ adc2: adc@100 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x100>;
+ interrupt-parent = <&adc_12>;
+ interrupts = <1>;
+ status = "disabled";
+ };
+ };
+
+ usbotg_hs: usb@40040000 {
+ compatible = "st,stm32f7-hsotg";
+ reg = <0x40040000 0x40000>;
+ interrupts = <77>;
+ clocks = <&rcc USB1OTG_CK>;
+ clock-names = "otg";
+ g-rx-fifo-size = <256>;
+ g-np-tx-fifo-size = <32>;
+ g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
+ status = "disabled";
+ };
+
+ usbotg_fs: usb@40080000 {
+ compatible = "st,stm32f4x9-fsotg";
+ reg = <0x40080000 0x40000>;
+ interrupts = <101>;
+ clocks = <&rcc USB2OTG_CK>;
+ clock-names = "otg";
+ status = "disabled";
+ };
+
+ mdma1: dma@52000000 {
+ compatible = "st,stm32h7-mdma";
+ reg = <0x52000000 0x1000>;
+ interrupts = <122>;
+ clocks = <&rcc MDMA_CK>;
+ #dma-cells = <5>;
+ dma-channels = <16>;
+ dma-requests = <32>;
+ };
+
+ exti: interrupt-controller@58000000 {
+ compatible = "st,stm32h7-exti";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x58000000 0x400>;
+ interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <62>, <76>;
+ };
+
+ syscfg: system-config@58000400 {
+ compatible = "syscon";
+ reg = <0x58000400 0x400>;
+ };
+
+ spi6: spi@58001400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32h7-spi";
+ reg = <0x58001400 0x400>;
+ interrupts = <86>;
+ clocks = <&rcc SPI6_CK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@58001C00 {
+ compatible = "st,stm32f7-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x58001C00 0x400>;
+ interrupts = <95>,
+ <96>;
+ resets = <&rcc STM32H7_APB4_RESET(I2C4)>;
+ clocks = <&rcc I2C4_CK>;
+ status = "disabled";
+ };
+
+ lptimer2: timer@58002400 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x58002400 0x400>;
+ clocks = <&rcc LPTIM2_CK>;
+ clock-names = "mux";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@1 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <1>;
+ status = "disabled";
+ };
+
+ counter {
+ compatible = "st,stm32-lptimer-counter";
+ status = "disabled";
+ };
+ };
+
+ lptimer3: timer@58002800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x58002800 0x400>;
+ clocks = <&rcc LPTIM3_CK>;
+ clock-names = "mux";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ trigger@2 {
+ compatible = "st,stm32-lptimer-trigger";
+ reg = <2>;
+ status = "disabled";
+ };
+ };
+
+ lptimer4: timer@58002c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x58002c00 0x400>;
+ clocks = <&rcc LPTIM4_CK>;
+ clock-names = "mux";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ };
+
+ lptimer5: timer@58003000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "st,stm32-lptimer";
+ reg = <0x58003000 0x400>;
+ clocks = <&rcc LPTIM5_CK>;
+ clock-names = "mux";
+ status = "disabled";
+
+ pwm {
+ compatible = "st,stm32-pwm-lp";
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+ };
+
+ vrefbuf: regulator@58003c00 {
+ compatible = "st,stm32-vrefbuf";
+ reg = <0x58003C00 0x8>;
+ clocks = <&rcc VREF_CK>;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <2500000>;
+ status = "disabled";
+ };
+
+ rtc: rtc@58004000 {
+ compatible = "st,stm32h7-rtc";
+ reg = <0x58004000 0x400>;
+ clocks = <&rcc RTCAPB_CK>, <&rcc RTC_CK>;
+ clock-names = "pclk", "rtc_ck";
+ assigned-clocks = <&rcc RTC_CK>;
+ assigned-clock-parents = <&rcc LSE_CK>;
+ interrupt-parent = <&exti>;
+ interrupts = <17 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "alarm";
+ st,syscfg = <&pwrcfg 0x00 0x100>;
+ status = "disabled";
+ };
+
+ rcc: reset-clock-controller@58024400 {
+ compatible = "st,stm32h743-rcc", "st,stm32-rcc";
+ reg = <0x58024400 0x400>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&clk_hse>, <&clk_lse>, <&clk_i2s>;
+ st,syscfg = <&pwrcfg>;
+ };
+
pwrcfg: power-config@58024800 {
compatible = "syscon";
reg = <0x58024800 0x400>;
};
- clk_hsi: clk-hsi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <64000000>;
- };
+ adc_3: adc@58026000 {
+ compatible = "st,stm32h7-adc-core";
+ reg = <0x58026000 0x400>;
+ interrupts = <127>;
+ clocks = <&rcc ADC3_CK>;
+ clock-names = "bus";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
- clk_csi: clk-csi {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <4000000>;
+ adc3: adc@0 {
+ compatible = "st,stm32h7-adc";
+ #io-channel-cells = <1>;
+ reg = <0x0>;
+ interrupt-parent = <&adc_3>;
+ interrupts = <0>;
+ status = "disabled";
+ };
};
};
};
diff --git a/arch/arm/dts/stm32h743i-disco.dts b/arch/arm/dts/stm32h743i-disco.dts
index 1237a81..45e088c 100644
--- a/arch/arm/dts/stm32h743i-disco.dts
+++ b/arch/arm/dts/stm32h743i-disco.dts
@@ -62,9 +62,12 @@
};
};
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
&usart2 {
pinctrl-0 = <&usart2_pins>;
pinctrl-names = "default";
status = "okay";
};
-
diff --git a/arch/arm/dts/stm32h743i-eval.dts b/arch/arm/dts/stm32h743i-eval.dts
index c8b6dfb..3f8e0c4 100644
--- a/arch/arm/dts/stm32h743i-eval.dts
+++ b/arch/arm/dts/stm32h743i-eval.dts
@@ -60,6 +60,48 @@
aliases {
serial0 = &usart1;
};
+
+ vdda: regulator-vdda {
+ compatible = "regulator-fixed";
+ regulator-name = "vdda";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ usbotg_hs_phy: usb-phy {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&rcc USB1ULPI_CK>;
+ clock-names = "main_clk";
+ };
+
+};
+
+&adc_12 {
+ vref-supply = <&vdda>;
+ status = "okay";
+ adc1: adc@0 {
+ /* potentiometer */
+ st,adc-channels = <0>;
+ status = "okay";
+ };
+};
+
+&clk_hse {
+ clock-frequency = <25000000>;
+};
+
+&i2c1 {
+ pinctrl-0 = <&i2c1_pins_a>;
+ pinctrl-names = "default";
+ i2c-scl-rising-time-ns = <185>;
+ i2c-scl-falling-time-ns = <20>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
};
&usart1 {
@@ -67,3 +109,12 @@
pinctrl-names = "default";
status = "okay";
};
+
+&usbotg_hs {
+ pinctrl-0 = <&usbotg_hs_pins_a>;
+ pinctrl-names = "default";
+ phys = <&usbotg_hs_phy>;
+ phy-names = "usb2-phy";
+ dr_mode = "otg";
+ status = "okay";
+};