commit 148241053123f3c2388d755807438fbe44dd2139
author Troy Kisky <troy.kisky@boundarydevices.com> Thu Mar 22 12:00:31 2012 +0000
committer Albert ARIBAUD <albert.u.boot@aribaud.net> Mon Apr 16 14:53:58 2012 +0200
tree 9fe038dbbe9cec28b1f9e6af030d9ee719eb2ac6
parent 607dfdf568baa506dc4ff33a38be3478820648fd

MX53: DDR: Fix ZQHWCTRL field TZQ_CS

Currently, board files are setting this field to 0x01
which the manual says is a reserved value. Change to
use the default of 0x02 - 128 cycles.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Fabio Estevam <fabio.estevam@freescale.com>

board/freescale/mx53ard/imximage_dd3.cfg

diff --git a/board/freescale/mx53ard/imximage_dd3.cfg b/board/freescale/mx53ard/imximage_dd3.cfg
index 50e05af..614d29e 100644
--- a/board/freescale/mx53ard/imximage_dd3.cfg
+++ b/board/freescale/mx53ard/imximage_dd3.cfg
@@ -91,6 +91,6 @@
 DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
 DATA 4 0x63fd9020 0x00005800
-DATA 4 0x63fd9040 0x04b80003
+DATA 4 0x63fd9040 0x05380003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901C 0x00000000