85xx: Fix the clock adjust of mpc8569mds board
Currently the clk_adj is 6 (3/4 cycle), The settings will cause
the DDR controller hang at the data init. Change the clk_adj
from 6 to 4 (1/2 cycle), make the memory system stable.
Signed-off-by: Dave Liu <daveliu@freescale.com>
diff --git a/board/freescale/mpc8569mds/ddr.c b/board/freescale/mpc8569mds/ddr.c
index 4b4533e..e938788 100644
--- a/board/freescale/mpc8569mds/ddr.c
+++ b/board/freescale/mpc8569mds/ddr.c
@@ -54,7 +54,7 @@
* 0110 3/4 cycle late
* 0111 7/8 cycle late
*/
- popts->clk_adjust = 6;
+ popts->clk_adjust = 4;
/*
* Factors to consider for CPO: