| commit | 1ba43d29eb626ee813650baf12a72a31ed2bffca | [log] [tgz] |
|---|---|---|
| author | Pragnesh Patel <pragnesh.patel@sifive.com> | Fri May 29 11:33:31 2020 +0530 |
| committer | Andes <uboot@andestech.com> | Thu Jun 04 09:44:09 2020 +0800 |
| tree | 75e44bd1e559f352c22db58aa48d1598028dcb1b | |
| parent | 378c7094afb0219ef11271e427f2e80753722ba8 [diff] |
clk: sifive: fu540-prci: Release ethernet clock reset U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>