[PATCH] Update Prodrive ALPR board support (440GX)
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/board/prodrive/alpr/Makefile b/board/prodrive/alpr/Makefile
index 1024a41..00dc180 100644
--- a/board/prodrive/alpr/Makefile
+++ b/board/prodrive/alpr/Makefile
@@ -25,7 +25,7 @@
LIB = $(obj)lib$(BOARD).a
-COBJS = $(BOARD).o flash.o fpga.o nand.o
+COBJS = $(BOARD).o fpga.o nand.o
SOBJS = init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
@@ -33,7 +33,7 @@
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
- $(AR) crv $@ $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index e8435bf..2389561 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -26,6 +26,7 @@
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
+#include <miiphy.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -33,24 +34,14 @@
int board_early_init_f (void)
{
- unsigned long mfr;
-
- /*-------------------------------------------------------------------------+
- | Initialize EBC CONFIG
- +-------------------------------------------------------------------------*/
-#if 0
- mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
- EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
- EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
- EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
- EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#else
+ /*-------------------------------------------------------------------------
+ * Initialize EBC CONFIG
+ *-------------------------------------------------------------------------*/
mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
-#endif
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
@@ -58,8 +49,8 @@
mtdcr (uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
- mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
- mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
+ mtdcr (uic0pr, 0xfffffe03); /* per manual */
+ mtdcr (uic0tr, 0x01c00000); /* per manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */
@@ -85,12 +76,57 @@
mtdcr (uicb0pr, 0xfc000000); /* */
mtdcr (uicb0tr, 0x00000000); /* */
mtdcr (uicb0vr, 0x00000001); /* */
- mfsdr (sdr_mfr, mfr);
- mfr &= ~SDR0_MFR_ECS_MASK;
+
+ /* Setup GPIO/IRQ multiplexing */
+ mtsdr(sdr_pfc0, 0x01a03e00);
return 0;
}
+int last_stage_init(void)
+{
+ unsigned short reg;
+
+ /*
+ * Configure LED's of both Marvell 88E1111 PHY's
+ *
+ * This has to be done after the 4xx ethernet driver is loaded,
+ * so "last_stage_init()" is the right place.
+ */
+ miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
+ miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, ®);
+ reg |= 0x0001;
+ miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
+
+ return 0;
+}
+
+static int board_rev(void)
+{
+ int rev;
+ u32 pfc0;
+
+ /* Setup GPIO14 & 15 as GPIO */
+ mfsdr(sdr_pfc0, pfc0);
+ pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
+ mtsdr(sdr_pfc0, pfc0);
+
+ /* Setup as input */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
+ out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
+
+ rev = (in32(GPIO0_IR) >> 16) & 0x3;
+
+ /* Setup GPIO14 & 15 as non GPIO again */
+ mfsdr(sdr_pfc0, pfc0);
+ pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
+ mtsdr(sdr_pfc0, pfc0);
+
+ return rev;
+}
+
int checkboard (void)
{
char *s = getenv ("serial#");
@@ -100,7 +136,7 @@
puts (", serial# ");
puts (s);
}
- putc ('\n');
+ printf(" (Rev. %d)\n", board_rev());
return (0);
}
@@ -224,10 +260,26 @@
*
************************************************************************/
#if defined(CONFIG_PCI)
+
+static void wait_for_pci_ready(void)
+{
+ /*
+ * Configure EREADY as input
+ */
+ out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+ udelay(1000);
+
+ for (;;) {
+ if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+ return;
+ }
+
+}
+
int is_pci_host(struct pci_controller *hose)
{
- /* The ocotea board is always configured as host. */
- return(1);
+ wait_for_pci_ready();
+ return 1; /* return 1 for host controller */
}
#endif /* defined(CONFIG_PCI) */
@@ -274,11 +326,3 @@
return (ctrlc());
}
#endif
-
-void board_reset(void)
-{
- /*
- * Initiate chip reset in debug control register DBCR
- */
- mtspr(dbcr0, 0x20000000);
-}
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
index 78307b4..e94360f 100644
--- a/board/prodrive/alpr/fpga.c
+++ b/board/prodrive/alpr/fpga.c
@@ -36,7 +36,7 @@
DECLARE_GLOBAL_DATA_PTR;
-#if (CONFIG_FPGA)
+#if defined(CONFIG_FPGA)
#ifdef FPGA_DEBUG
#define PRINTF(fmt,args...) printf (fmt ,##args)
@@ -44,46 +44,38 @@
#define PRINTF(fmt,args...)
#endif
-static unsigned long regval;
+static unsigned long regval;
-#define SET_GPIO_REG_0(reg, bit) {\
- regval = in32(reg);\
- regval &= ~(0x80000000 >> bit);\
- out32(reg, regval);\
- }
+#define SET_GPIO_REG_0(reg, bit) { \
+ regval = in32(reg); \
+ regval &= ~(0x80000000 >> bit); \
+ out32(reg, regval); \
+ }
-#define SET_GPIO_REG_1(reg, bit) {\
- regval = in32(reg);\
- regval |= (0x80000000 >> bit);\
- out32(reg, regval);\
- }
+#define SET_GPIO_REG_1(reg, bit) { \
+ regval = in32(reg); \
+ regval |= (0x80000000 >> bit); \
+ out32(reg, regval); \
+ }
-#define GPIO_CLK_PIN 0x00002000
-#define GPIO_CLK_PIN_I 0xffffdfff
-#define GPIO_DAT_PIN 0x00001000
-#define GPIO_DAT_PIN_I 0xffffefff
-#define GPIO_CLKDAT_PIN_I 0xffffcfff
+#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
+#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
-#define SET_GPIO_CLK_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLK_PIN_I);
-#define SET_GPIO_CLK_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_CLK_PIN);
-#define SET_GPIO_DAT_0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_DAT_PIN_I);
-#define SET_GPIO_DAT_1 out32(GPIO0_OR, in32(GPIO0_OR) | GPIO_DAT_PIN);
+#define FPGA_PRG (0x80000000 >> CFG_GPIO_PROG_EN)
+#define FPGA_CONFIG (0x80000000 >> CFG_GPIO_CONFIG)
+#define FPGA_DATA (0x80000000 >> CFG_GPIO_DATA)
+#define FPGA_CLK (0x80000000 >> CFG_GPIO_CLK)
+#define OLD_VAL (FPGA_PRG | FPGA_CONFIG)
-#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
-#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
+#define SET_FPGA(data) out32(GPIO0_OR, data)
-#define SET_GPIO_CLK_0_Z1 out32(GPIO0_OR, (in32(GPIO0_OR) & GPIO_CLK_PIN_I) | GPIO_DAT_PIN);
-#define SET_GPIO_CLK_0_Z0 out32(GPIO0_OR, in32(GPIO0_OR) & GPIO_CLKDAT_PIN_I);
+#define FPGA_WRITE_1 { \
+ SET_FPGA(OLD_VAL | 0 | FPGA_DATA); /* set data to 1 */ \
+ SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
-#define FPGA_WRITE_1 { \
- SET_GPIO_CLK_0_Z1\
- SET_GPIO_CLK_1}
-
-#define FPGA_WRITE_0 { \
- SET_GPIO_CLK_0_Z0\
- SET_GPIO_CLK_1}
-
-#define P_GP(reg) (reg & 0x00023f00)
+#define FPGA_WRITE_0 { \
+ SET_FPGA(OLD_VAL | 0 | 0 ); /* set data to 0 */ \
+ SET_FPGA(OLD_VAL | FPGA_CLK | 0 );} /* set data to 1 */
/* Plattforminitializations */
/* Here we have to set the FPGA Chain */
@@ -102,7 +94,7 @@
SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
SET_GPIO_0((CFG_GPIO_SEL_DPR));
- /* initialize the GPIO Pins */
+ /* initialize the GPIO Pins */
/* output */
SET_GPIO_0(CFG_GPIO_CLK);
SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
@@ -174,7 +166,7 @@
}
/* writes the complete buffer to the FPGA
- writing the complete buffer in one function is very faster,
+ writing the complete buffer in one function is much faster,
then calling it for every bit */
int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
{
@@ -182,14 +174,10 @@
unsigned char *data = (unsigned char *) buf;
unsigned char val=0;
int i;
+ int len_40 = len / 40;
while (bytecount < len) {
-#ifdef CFG_FPGA_CHECK_CTRLC
- if (ctrlc ()) {
- return FPGA_FAIL;
- }
-#endif
- val = data[bytecount ++ ];
+ val = data[bytecount++];
i = 8;
do {
if (val & 0x01) {
@@ -202,8 +190,13 @@
} while (i > 0);
#ifdef CFG_FPGA_PROG_FEEDBACK
- if (bytecount % (len / 40) == 0)
+ if (bytecount % len_40 == 0) {
putc ('.'); /* let them know we are alive */
+#ifdef CFG_FPGA_CHECK_CTRLC
+ if (ctrlc ())
+ return FPGA_FAIL;
+#endif
+ }
#endif
}
return FPGA_SUCCESS;
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 1baa609..135674c 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -34,7 +34,6 @@
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
-#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 20a8098..e63c921 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -32,19 +32,19 @@
#include <nand.h>
struct alpr_ndfc_regs {
- u16 cmd[4];
- u16 addr_wait;
- u16 term;
- u16 dummy;
- u16 dummy2;
- u16 data;
+ u8 cmd[4];
+ u8 addr_wait;
+ u8 term;
+ u8 dummy;
+ u8 dummy2;
+ u8 data;
};
static u8 hwctl;
static struct alpr_ndfc_regs *alpr_ndfc = NULL;
-#define readb(addr) (u8)(*(volatile u16 *)(addr))
-#define writeb(d,addr) *(volatile u16 *)(addr) = ((u16)(d))
+#define readb(addr) (u8)(*(volatile u8 *)(addr))
+#define writeb(d,addr) *(volatile u8 *)(addr) = ((u8)(d))
/*
* The ALPR has a NAND Flash Controller (NDFC) that handles all accesses to
diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c
index 81d49ff..8c517ba 100644
--- a/cpu/ppc4xx/4xx_enet.c
+++ b/cpu/ppc4xx/4xx_enet.c
@@ -470,8 +470,7 @@
#else
if ((devnum == 0) || (devnum == 1)) {
out32 (ZMII_FER, (ZMII_FER_SMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
- }
- else { /* ((devnum == 2) || (devnum == 3)) */
+ } else { /* ((devnum == 2) || (devnum == 3)) */
out32 (ZMII_FER, ZMII_FER_MDI << ZMII_FER_V (devnum));
out32 (RGMII_FER, ((RGMII_FER_RGMII << RGMII_FER_V (2)) |
(RGMII_FER_RGMII << RGMII_FER_V (3))));
@@ -808,7 +807,7 @@
hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
hw_p->rx_ready[i] = -1;
#if 0
- printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
+ printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) hw_p->rx[i].data_ptr);
#endif
}
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c
index faa5257..c45525d 100644
--- a/cpu/ppc4xx/cpu.c
+++ b/cpu/ppc4xx/cpu.c
@@ -426,8 +426,8 @@
int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
-#if defined(CONFIG_BOARD_RESET)
- board_reset();
+#if defined(CFG_4xx_RESET_TYPE)
+ mtspr(dbcr0, CFG_4xx_RESET_TYPE << 28);
#else
/*
* Initiate system reset in debug control register DBCR
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c
index def46f1..4b746b0 100644
--- a/cpu/ppc4xx/cpu_init.c
+++ b/cpu/ppc4xx/cpu_init.c
@@ -321,6 +321,10 @@
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif
+#if defined(CFG_4xx_RESET_TYPE)
+ val &= ~0x30000000; /* clear WRC bits */
+ val |= CFG_4xx_RESET_TYPE << 28; /* set board specific WRC type */
+#endif
mtspr(tcr, val);
val = mfspr(tsr);
diff --git a/include/configs/alpr.h b/include/configs/alpr.h
index c6731ba..60da820 100644
--- a/include/configs/alpr.h
+++ b/include/configs/alpr.h
@@ -31,25 +31,25 @@
#define CONFIG_440GX 1 /* Specifc GX support */
#define CONFIG_4xx 1 /* ... PPC4xx family */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
-#define CONFIG_BOARD_RESET 1 /* call board_reset() */
+#define CONFIG_LAST_STAGE_INIT 1 /* call last_stage_init() */
#undef CFG_DRAM_TEST /* Disable-takes long time! */
-#define CONFIG_SYS_CLK_FREQ 33333000 /* external freq to pll */
+#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
/*-----------------------------------------------------------------------
* Base addresses -- Note these are effective addresses where the
* actual resources get mapped (not physical addresses)
*----------------------------------------------------------------------*/
-#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
-#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
-#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
-#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
-#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
-#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
-#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
-#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
-#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
-#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
-#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
+#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
+#define CFG_FLASH_BASE 0xffe00000 /* start of FLASH */
+#define CFG_MONITOR_BASE 0xfffc0000 /* start of monitor */
+#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
+#define CFG_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */
+#define CFG_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */
+#define CFG_ISRAM_BASE 0xc0000000 /* internal SRAM */
+#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
+#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
+#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000
+#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000
#define CFG_FPGA_BASE (CFG_PERIPHERAL_BASE + 0x08300000)
@@ -84,26 +84,13 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
-#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
-
+#define CFG_FLASH_CFI 1 /* The flash is CFI compatible */
+#define CFG_FLASH_CFI_DRIVER 1 /* Use common CFI driver */
#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
-#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
-#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
-
+#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
+#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
+#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
@@ -154,7 +141,7 @@
#undef CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
+ "netdev=eth3\0" \
"hostname=alpr\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
@@ -162,18 +149,19 @@
"addip=setenv bootargs ${bootargs} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
+ "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate} " \
+ "mem=193M\0" \
"flash_nfs=run nfsargs addip addtty;" \
"bootm ${kernel_addr}\0" \
"flash_self=run ramargs addip addtty;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
"bootm\0" \
- "rootpath=/opt/eldk/ppc_4xx\0" \
- "bootfile=/tftpboot/alpr/uImage\0" \
+ "rootpath=/opt/projects/alpr/nfs_root\0" \
+ "bootfile=/alpr/uImage\0" \
"kernel_addr=fff00000\0" \
"ramdisk_addr=fff10000\0" \
- "load=tftp 100000 /tftpboot/alpr/u-boot.bin\0" \
+ "load=tftp 100000 /alpr/u-boot/u-boot.bin\0" \
"update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
"cp.b 100000 fffc0000 40000;" \
"setenv filesize;saveenv\0" \
@@ -181,7 +169,7 @@
""
#define CONFIG_BOOTCOMMAND "run flash_self"
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#define CONFIG_BOOTDELAY 2 /* autoboot after 5 seconds */
#define CONFIG_BAUDRATE 115200
@@ -192,8 +180,8 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0x02 /* dummy setting, no EMAC0 used */
#define CONFIG_PHY1_ADDR 0x03 /* dummy setting, no EMAC1 used */
-#define CONFIG_PHY2_ADDR 0x00 /* test-only: will be changed */
-#define CONFIG_PHY3_ADDR 0x01 /* PHY address for EMAC3 */
+#define CONFIG_PHY2_ADDR 0x01 /* PHY address for EMAC2 */
+#define CONFIG_PHY3_ADDR 0x02 /* PHY address for EMAC3 */
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
@@ -251,9 +239,11 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
+#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
+
+#define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
/*-----------------------------------------------------------------------
* PCI stuff
@@ -264,7 +254,7 @@
#define CONFIG_PCI_PNP /* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
-#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
@@ -276,11 +266,10 @@
/*-----------------------------------------------------------------------
* FPGA stuff
- *-----------------------------------------------------------------------
- */
+ *-----------------------------------------------------------------------*/
#define CONFIG_FPGA CFG_ALTERA_CYCLON2
-#undef CFG_FPGA_CHECK_CTRLC
-#undef CFG_FPGA_PROG_FEEDBACK
+#define CFG_FPGA_CHECK_CTRLC
+#define CFG_FPGA_PROG_FEEDBACK
#define CONFIG_FPGA_COUNT 1 /* Ich habe 2 ... aber in
Reihe geschaltet -> sollte gehen,
aufpassen mit Datasize ist jetzt
@@ -299,9 +288,16 @@
#define CFG_GPIO_SEL_AVR 15 /* cpu output */
#define CFG_GPIO_PROG_EN 23 /* cpu output */
-/*
+/*-----------------------------------------------------------------------
+ * Definitions for GPIO setup
+ *-----------------------------------------------------------------------*/
+#define CFG_GPIO_EREADY (0x80000000 >> 26)
+#define CFG_GPIO_REV0 (0x80000000 >> 14)
+#define CFG_GPIO_REV1 (0x80000000 >> 15)
+
+/*-----------------------------------------------------------------------
* NAND-FLASH stuff
- */
+ *-----------------------------------------------------------------------*/
#define CFG_MAX_NAND_DEVICE 4
#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE
#define CFG_NAND_BASE 0xF0000000 /* NAND FLASH Base Address */
@@ -320,7 +316,7 @@
/* Memory Bank 1 (NAND-FLASH) initialization */
#define CFG_EBC_PB1AP 0x01840380 /* TWT=3 */
-#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x1A000) /* BS=1MB,BU=R/W,BW=16bit */
+#define CFG_EBC_PB1CR (CFG_NAND_BASE | 0x18000) /* BS=1MB,BU=R/W,BW=8bit */
/*
* For booting Linux, the board info and command line data
@@ -333,9 +329,7 @@
*/
#define CFG_DCACHE_SIZE 32768 /* For AMCC 440 CPUs */
#define CFG_CACHELINE_SIZE 32 /* ... */
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
/*
* Internal Definitions