arch: powerpc: update the IFC IP input clock
IFC IP clock is always a constant divisor of platform clock
pre-defined per SoC. Clock control register (CCR) used in
current implementation governs IFC IP output clock.
Update sys_info->freq_localbus to represent IFC input clock with
value constant divisor of platform clock.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
diff --git a/README b/README
index a95348a..9fda381 100644
--- a/README
+++ b/README
@@ -504,6 +504,9 @@
CONFIG_SYS_FSL_IFC_LE
Defines the IFC controller register space as Little Endian
+ CONFIG_SYS_FSL_IFC_CLK_DIV
+ Defines divider of platform clock(clock input to IFC controller).
+
CONFIG_SYS_FSL_PBL_PBI
It enables addition of RCW (Power on reset configuration) in built image.
Please refer doc/README.pblimage for more details