commit 1e4d99549f00de502fe02b0bbed16327434e2514
author Dario Binacchi <dario.binacchi@amarulasolutions.com> Sun Sep 03 22:48:49 2023 +0200
committer Patrice Chotard <patrice.chotard@foss.st.com> Wed Oct 04 13:26:02 2023 +0200
tree e129c76c85f8a3c731c7296c5bb679e70a2b03bd
parent f0c76e773148607fe4b990196538afb13e4224e6

ARM: dts: stm32: support display on stm32f746-disco board

The patch applies the changes from Linux commit 10a970bc3ebfa ("ARM: dts:
stm32: support display on stm32f746-disco board") and removes the same
settings from stm32f746-disco-u-boot.dtsi.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>

arch/arm/dts/stm32f746-disco-u-boot.dtsi

diff --git a/arch/arm/dts/stm32f746-disco-u-boot.dtsi b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
index 3c2b9fc..1b42d6c 100644
--- a/arch/arm/dts/stm32f746-disco-u-boot.dtsi
+++ b/arch/arm/dts/stm32f746-disco-u-boot.dtsi
@@ -23,12 +23,6 @@
 		spi0 = &qspi;
 	};
 
-	backlight: backlight {
-		compatible = "gpio-backlight";
-		gpios = <&gpiok 3 0>;
-		status = "okay";
-	};
-
 	button1 {
 		compatible = "st,button1";
 		button-gpio = <&gpioi 11 0>;
@@ -38,37 +32,10 @@
 		compatible = "st,led1";
 		led-gpio = <&gpioi 1 0>;
 	};
-
-	panel-rgb@0 {
-		compatible = "simple-panel";
-		backlight = <&backlight>;
-		enable-gpios = <&gpioi 12 0>;
-		status = "okay";
-
-		display-timings {
-			timing@0 {
-				clock-frequency = <9000000>;
-				hactive = <480>;
-				vactive = <272>;
-				hfront-porch = <2>;
-				hback-porch = <2>;
-				hsync-len = <41>;
-				vfront-porch = <2>;
-				vback-porch = <2>;
-				vsync-len = <10>;
-				hsync-active = <0>;
-				vsync-active = <0>;
-				de-active = <1>;
-				pixelclk-active = <1>;
-			};
-		};
-	};
 };
 
 &ltdc {
 	clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
-	pinctrl-0 = <&ltdc_pins>;
-	status = "okay";
 	bootph-all;
 };
 
@@ -96,6 +63,28 @@
 	};
 };
 
+&panel_rgb {
+	compatible = "simple-panel";
+
+	display-timings {
+		timing@0 {
+			clock-frequency = <9000000>;
+			hactive = <480>;
+			vactive = <272>;
+			hfront-porch = <2>;
+			hback-porch = <2>;
+			hsync-len = <41>;
+			vfront-porch = <2>;
+			vback-porch = <2>;
+			vsync-len = <10>;
+			hsync-active = <0>;
+			vsync-active = <0>;
+			de-active = <1>;
+			pixelclk-active = <1>;
+		};
+	};
+};
+
 &pinctrl {
 	ethernet_mii: mii@0 {
 		pins {
@@ -160,40 +149,6 @@
 		};
 	};
 
-	ltdc_pins: ltdc@0 {
-		pins {
-			pinmux = <STM32_PINMUX('E', 4, AF14)>, /* B0 */
-				 <STM32_PINMUX('G',12, AF9)>,  /* B4 */
-				 <STM32_PINMUX('I', 9, AF14)>, /* VSYNC */
-				 <STM32_PINMUX('I',10, AF14)>, /* HSYNC */
-				 <STM32_PINMUX('I',14, AF14)>, /* CLK */
-				 <STM32_PINMUX('I',15, AF14)>, /* R0 */
-				 <STM32_PINMUX('J', 0, AF14)>, /* R1 */
-				 <STM32_PINMUX('J', 1, AF14)>, /* R2 */
-				 <STM32_PINMUX('J', 2, AF14)>, /* R3 */
-				 <STM32_PINMUX('J', 3, AF14)>, /* R4 */
-				 <STM32_PINMUX('J', 4, AF14)>, /* R5 */
-				 <STM32_PINMUX('J', 5, AF14)>, /* R6 */
-				 <STM32_PINMUX('J', 6, AF14)>, /* R7 */
-				 <STM32_PINMUX('J', 7, AF14)>, /* G0 */
-				 <STM32_PINMUX('J', 8, AF14)>, /* G1 */
-				 <STM32_PINMUX('J', 9, AF14)>, /* G2 */
-				 <STM32_PINMUX('J',10, AF14)>, /* G3 */
-				 <STM32_PINMUX('J',11, AF14)>, /* G4 */
-				 <STM32_PINMUX('J',13, AF14)>, /* B1 */
-				 <STM32_PINMUX('J',14, AF14)>, /* B2 */
-				 <STM32_PINMUX('J',15, AF14)>, /* B3 */
-				 <STM32_PINMUX('K', 0, AF14)>, /* G5 */
-				 <STM32_PINMUX('K', 1, AF14)>, /* G6 */
-				 <STM32_PINMUX('K', 2, AF14)>, /* G7 */
-				 <STM32_PINMUX('K', 4, AF14)>, /* B5 */
-				 <STM32_PINMUX('K', 5, AF14)>, /* B6 */
-				 <STM32_PINMUX('K', 6, AF14)>, /* B7 */
-				 <STM32_PINMUX('K', 7, AF14)>; /* DE */
-			slew-rate = <2>;
-		};
-	};
-
 	qspi_pins: qspi@0 {
 		pins {
 			pinmux = <STM32_PINMUX('B', 2, AF9)>, /* CLK */