| commit | 1f293b417ac6ab8e317ca2b770377ca93edf2370 | [log] [tgz] |
|---|---|---|
| author | Haiying Wang <Haiying.Wang@freescale.com> | Fri Oct 03 12:37:26 2008 -0400 |
| committer | Wolfgang Denk <wd@denx.de> | Sat Oct 18 21:54:05 2008 +0200 |
| tree | 6915cd565889166c69253d825e384a354e8c052e | |
| parent | c9ffd839b1ada502c86f88edaf1534426b6688ce [diff] |
Add debug information for DDR controller registers Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>