| commit | 9343dbf85bc03033f2102d8e8543567c2c1ad2d2 | [log] [tgz] |
|---|---|---|
| author | Andy Fleming <afleming@freescale.com> | Sat Feb 24 01:16:45 2007 -0600 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Mon Apr 23 19:58:28 2007 -0500 |
| tree | 94edfc80e63eb36793f6feed2c46339e0cfb9cce | |
| parent | 85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b [diff] |
Tweak DDR ECC error counter Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>