pm9263 converted to at91 soc access
Signed-off-by: Asen Dimov <dimov@ronetix.at>
diff --git a/board/ronetix/pm9263/pm9263.c b/board/ronetix/pm9263/pm9263.c
index 23ea154..c7835de 100644
--- a/board/ronetix/pm9263/pm9263.c
+++ b/board/ronetix/pm9263/pm9263.c
@@ -27,13 +27,13 @@
#include <common.h>
#include <asm/sizes.h>
#include <asm/arch/at91sam9263.h>
-#include <asm/arch/at91sam9263_matrix.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_rstc.h>
+#include <asm/arch/at91_matrix.h>
+#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/arch/hardware.h>
#include <lcd.h>
@@ -55,52 +55,59 @@
static void pm9263_nand_hw_init(void)
{
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC0_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 */
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA,
- csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+ csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
+ writel(csa, &matrix->csa[0]);
/* Configure SMC CS3 for NAND/SmartMedia */
- at91_sys_write(AT91_SMC_SETUP(3),
- AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(1) |
- AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(1));
- at91_sys_write(AT91_SMC_PULSE(3),
- AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
- AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
- at91_sys_write(AT91_SMC_CYCLE(3),
- AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
- at91_sys_write(AT91_SMC_MODE(3),
- AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
- AT91_SMC_EXNWMODE_DISABLE |
+ writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
+ AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
+ &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
+ AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+ AT91_SMC_MODE_EXNW_DISABLE |
#ifdef CONFIG_SYS_NAND_DBW_16
- AT91_SMC_DBW_16 |
+ AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
- AT91_SMC_DBW_8 |
+ AT91_SMC_MODE_DBW_8 |
#endif
- AT91_SMC_TDF_(2));
+ AT91_SMC_MODE_TDF_CYCLE(2),
+ &smc->cs[3].mode);
/* Configure RDY/BSY */
- at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_set_pio_input(CONFIG_SYS_NAND_READY_PIN, 1);
/* Enable NandFlash */
- at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ at91_set_pio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
}
#endif
#ifdef CONFIG_MACB
static void pm9263_macb_hw_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+ at91_pio_t *pio = (at91_pio_t *) AT91_PIO_BASE;
+
/*
* PB27 enables the 50MHz oscillator for Ethernet PHY
* 1 - enable
* 0 - disable
*/
- at91_set_gpio_output(AT91_PIN_PB27, 1);
- at91_set_gpio_value(AT91_PIN_PB27, 1); /* 1- enable, 0 - disable */
+ at91_set_pio_output(AT91_PIO_PORTB, 27, 1);
+ at91_set_pio_value(AT91_PIO_PORTB, 27, 1); /* 1- enable, 0 - disable */
/* Enable clock */
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+ writel(1 << AT91SAM9263_ID_EMAC, &pmc->pcer);
/*
* Disable pull-up on:
@@ -110,19 +117,15 @@
*
* PHY has internal pull-down
*/
- writel(pin_to_mask(AT91_PIN_PC25),
- pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
- writel(pin_to_mask(AT91_PIN_PE25) |
- pin_to_mask(AT91_PIN_PE26),
- pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
+ at91_set_pio_pullup(AT91_PIO_PORTC, 25, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 25, 0);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 26, 0);
/* Re-enable pull-up */
- writel(pin_to_mask(AT91_PIN_PC25),
- pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
- writel(pin_to_mask(AT91_PIN_PE25) |
- pin_to_mask(AT91_PIN_PE26),
- pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
+ at91_set_pio_pullup(AT91_PIO_PORTC, 25, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 25, 1);
+ at91_set_pio_pullup(AT91_PIO_PORTE, 26, 1);
at91_macb_hw_init();
}
@@ -148,17 +151,17 @@
void lcd_enable(void)
{
- at91_set_gpio_value(AT91_PIN_PA22, 1); /* power up */
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 1); /* power up */
}
void lcd_disable(void)
{
- at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
}
#ifdef CONFIG_LCD_IN_PSRAM
-#define PSRAM_CRE_PIN AT91_PIN_PB29
+#define PSRAM_CRE_PIN AT91_PIO_PORTB, 29
#define PSRAM_CTRL_REG (PHYS_PSRAM + PHYS_PSRAM_SIZE - 2)
/* Initialize the PSRAM memory */
@@ -166,31 +169,34 @@
{
volatile uint16_t x;
unsigned long csa;
+ at91_smc_t *smc = (at91_smc_t *) AT91_SMC1_BASE;
+ at91_matrix_t *matrix = (at91_matrix_t *) AT91_MATRIX_BASE;
/* Enable CS3 3.3v, no pull-ups */
- csa = at91_sys_read(AT91_MATRIX_EBI1CSA);
- at91_sys_write(AT91_MATRIX_EBI1CSA,
- csa | AT91_MATRIX_EBI1_DBPUC |
- AT91_MATRIX_EBI1_VDDIOMSEL_3_3V);
+ csa = readl(&matrix->csa[1]) | AT91_MATRIX_CSA_DBPUC |
+ AT91_MATRIX_CSA_VDDIOMSEL_3_3V;
+
+ writel(csa, &matrix->csa[1]);
/* Configure SMC1 CS0 for PSRAM - 16-bit */
- at91_sys_write(AT91_SMC1_SETUP(0),
- AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
- AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
- at91_sys_write(AT91_SMC1_PULSE(0),
- AT91_SMC_NWEPULSE_(7) | AT91_SMC_NCS_WRPULSE_(7) |
- AT91_SMC_NRDPULSE_(2) | AT91_SMC_NCS_RDPULSE_(7));
- at91_sys_write(AT91_SMC1_CYCLE(0),
- AT91_SMC_NWECYCLE_(8) | AT91_SMC_NRDCYCLE_(8));
- at91_sys_write(AT91_SMC1_MODE(0),
- AT91_SMC_DBW_16 |
- AT91_SMC_PMEN |
- AT91_SMC_PS_32);
+ writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
+ AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
+ &smc->cs[0].setup);
+
+ writel(AT91_SMC_PULSE_NWE(7) | AT91_SMC_PULSE_NCS_WR(7) |
+ AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(7),
+ &smc->cs[0].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(8) | AT91_SMC_CYCLE_NRD(8),
+ &smc->cs[0].cycle);
+
+ writel(AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_PMEN | AT91_SMC_MODE_PS_32,
+ &smc->cs[0].mode);
/* setup PB29 as output */
- at91_set_gpio_output(PSRAM_CRE_PIN, 1);
+ at91_set_pio_output(PSRAM_CRE_PIN, 1);
- at91_set_gpio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
+ at91_set_pio_value(PSRAM_CRE_PIN, 0); /* set PSRAM_CRE_PIN to '0' */
/* PSRAM: write BCR */
x = readw(PSRAM_CTRL_REG);
@@ -216,7 +222,7 @@
/* test if the chip is MT45W2M16B */
if ((readw(PHYS_PSRAM) != 0x1234) || (readw(PHYS_PSRAM+2) != 0x5678)) {
/* try with CRE=1 (MT45W2M16A) */
- at91_set_gpio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
+ at91_set_pio_value(PSRAM_CRE_PIN, 1); /* set PSRAM_CRE_PIN to '1' */
/* write RCR of the PSRAM */
x = readw(PSRAM_CTRL_REG);
@@ -229,17 +235,14 @@
writew(0x1234, PHYS_PSRAM);
writew(0x5678, PHYS_PSRAM+2);
if ((readw(PHYS_PSRAM) != 0x1234)
- || (readw(PHYS_PSRAM + 2) != 0x5678))
+ || (readw(PHYS_PSRAM + 2) != 0x5678))
return 1;
}
/* Bus matrix */
- at91_sys_write( AT91_MATRIX_PRAS5, AT91_MATRIX_M5PR );
- at91_sys_write( AT91_MATRIX_SCFG5, AT91_MATRIX_ARBT_FIXED_PRIORITY |
- (AT91_MATRIX_FIXED_DEFMSTR & (5 << 18)) |
- AT91_MATRIX_DEFMSTR_TYPE_FIXED |
- (AT91_MATRIX_SLOT_CYCLE & (0xFF << 0)));
+ writel(AT91_MATRIX_PRA_M5(3), &matrix->pr[5].a);
+ writel(CONFIG_PSRAM_SCFG, &matrix->scfg[5]);
return 0;
}
@@ -247,35 +250,37 @@
static void pm9263_lcd_hw_init(void)
{
- at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
- at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
- at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
- at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
- at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
- at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
- at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
- at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
- at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
- at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
- at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
- at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
- at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
- at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
- at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
- at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
- at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
- at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
- at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
- at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
- at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
- at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
- at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
- at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0); /* LCDVSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0); /* LCDHSYNC */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0); /* LCDDOTCK */
+ at91_set_a_periph(AT91_PIO_PORTC, 3, 0); /* LCDDEN */
+ at91_set_b_periph(AT91_PIO_PORTB, 9, 0); /* LCDCC */
+ at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* LCDD2 */
+ at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* LCDD3 */
+ at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* LCDD4 */
+ at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* LCDD5 */
+ at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* LCDD6 */
+ at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* LCDD7 */
+ at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* LCDD10 */
+ at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* LCDD11 */
+ at91_set_a_periph(AT91_PIO_PORTC, 16, 0); /* LCDD12 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 0); /* LCDD13 */
+ at91_set_a_periph(AT91_PIO_PORTC, 18, 0); /* LCDD14 */
+ at91_set_a_periph(AT91_PIO_PORTC, 19, 0); /* LCDD15 */
+ at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD18 */
+ at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD19 */
+ at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDD20 */
+ at91_set_b_periph(AT91_PIO_PORTC, 17, 0); /* LCDD21 */
+ at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDD22 */
+ at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDD23 */
+
+ writel(1 << AT91SAM9263_ID_LCDC, &pmc->pcer);
/* Power Control */
- at91_set_gpio_output(AT91_PIN_PA22, 1);
- at91_set_gpio_value(AT91_PIN_PA22, 0); /* power down */
+ at91_set_pio_output(AT91_PIO_PORTA, 22, 1);
+ at91_set_pio_value(AT91_PIO_PORTA, 22, 0); /* power down */
#ifdef CONFIG_LCD_IN_PSRAM
/* initialize te PSRAM */
@@ -337,13 +342,15 @@
int board_init(void)
{
+ at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
+
/* Enable Ctrlc */
console_init_f();
- at91_sys_write(AT91_PMC_PCER,
- (1 << AT91SAM9263_ID_PIOA) |
- (1 << AT91SAM9263_ID_PIOCDE) |
- (1 << AT91SAM9263_ID_PIOB));
+ writel((1 << AT91SAM9263_ID_PIOA) |
+ (1 << AT91SAM9263_ID_PIOCDE) |
+ (1 << AT91SAM9263_ID_PIOB),
+ &pmc->pcer);
/* arch number of AT91SAM9263EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_PM9263;
@@ -394,7 +401,7 @@
{
int rc = 0;
#ifdef CONFIG_MACB
- rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x01);
+ rc = macb_eth_initialize(0, (void *)AT91_EMAC_BASE, 0x01);
#endif
return rc;
}