commit 20edd1ac7ae7d081078dd64ffe7a89f48c09fd65
author Simon Glass <sjg@chromium.org> Fri Jun 05 14:39:35 2015 -0600
committer Tom Warren <twarren@nvidia.com> Tue Jun 09 09:56:13 2015 -0700
tree b434d873b314cfbf893109708afb36a6d9c529ea
parent b3b9d7ca324429319df1d1f246643d2ae928beb6

tegra: spi: Support slow SPI rates

Use the oscillator as the source clock when we cannot achieve a low-enough
speed with the peripheral clock. This happens when we request 3MHz on a SPI
clock, for example.

Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>

drivers/spi/tegra114_spi.c

diff --git a/drivers/spi/tegra114_spi.c b/drivers/spi/tegra114_spi.c
index 0d69376..d7eecd5 100644
--- a/drivers/spi/tegra114_spi.c
+++ b/drivers/spi/tegra114_spi.c
@@ -144,6 +144,7 @@
 	struct tegra_spi_platdata *plat = dev_get_platdata(bus);
 	struct tegra114_spi_priv *priv = dev_get_priv(bus);
 	struct spi_regs *regs;
+	ulong rate;
 
 	priv->regs = (struct spi_regs *)plat->base;
 	regs = priv->regs;
@@ -152,9 +153,20 @@
 	priv->freq = plat->frequency;
 	priv->periph_id = plat->periph_id;
 
-	/* Change SPI clock to correct frequency, PLLP_OUT0 source */
-	clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
-			       priv->freq);
+	/*
+	 * Change SPI clock to correct frequency, PLLP_OUT0 source, falling
+	 * back to the oscillator if that is too fast.
+	 */
+	rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
+				      priv->freq);
+	if (rate > priv->freq + 100000) {
+		rate = clock_start_periph_pll(priv->periph_id, CLOCK_ID_OSC,
+					      priv->freq);
+		if (rate != priv->freq) {
+			printf("Warning: SPI '%s' requested clock %u, actual clock %lu\n",
+			       bus->name, priv->freq, rate);
+		}
+	}
 
 	/* Clear stale status here */
 	setbits_le32(&regs->fifo_status,