| commit | 4d4222d07432faffe3a0fe35c483e116a28eb217 | [log] [tgz] |
|---|---|---|
| author | Zong Li <zong.li@sifive.com> | Wed Sep 01 15:01:40 2021 +0800 |
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | Tue Sep 07 10:34:29 2021 +0800 |
| tree | d231a09a9223c329f6b3dde902a43695e2c96e26 | |
| parent | 43a21839285c1ba3b65534def898a2b5e2d46314 [diff] |
common: board_r: support enable_caches for RISC-V The enable_caches is a generic hook for architecture-implemented, we leverage this function to enable caches for RISC-V Signed-off-by: Zong Li <zong.li@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>