rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff --git a/drivers/clk/rockchip/clk_rk3036.c b/drivers/clk/rockchip/clk_rk3036.c
index 514ea88..83f4ae6 100644
--- a/drivers/clk/rockchip/clk_rk3036.c
+++ b/drivers/clk/rockchip/clk_rk3036.c
@@ -249,8 +249,9 @@
/* mmc clock auto divide 2 in internal */
src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
- if (src_clk_div > 0x7f) {
+ if (src_clk_div > 128) {
src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
+ assert(src_clk_div - 1 < 128);
mux = EMMC_SEL_24M;
} else {
mux = EMMC_SEL_GPLL;