MPC85xx: Add MPC8569 CPU support
There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of
LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage,
then invalidate it after LBCR bit 13 is set.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h
index 094fb9c..0810b8e 100644
--- a/include/asm-ppc/immap_85xx.h
+++ b/include/asm-ppc/immap_85xx.h
@@ -1609,8 +1609,19 @@
char res2[12];
uint gpiocr; /* 0xe0030 - GPIO control register */
char res3[12];
+#if defined(CONFIG_MPC8569)
+ uint plppar1;
+ /* 0xe0040 - Platform port pin assignment register 1 */
+ uint plppar2;
+ /* 0xe0044 - Platform port pin assignment register 2 */
+ uint plpdir1;
+ /* 0xe0048 - Platform port pin direction register 1 */
+ uint plpdir2;
+ /* 0xe004c - Platform port pin direction register 2 */
+#else
uint gpoutdr; /* 0xe0040 - General-purpose output data register */
char res4[12];
+#endif
uint gpindr; /* 0xe0050 - General-purpose input data register */
char res5[12];
uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */
@@ -1651,7 +1662,7 @@
uint svr; /* 0xe00a4 - System version register */
char res10a[8];
uint rstcr; /* 0xe00b0 - Reset control register */
-#ifdef CONFIG_MPC8568
+#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
char res10b[76];
par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */
char res10c[3136];