| commit | 22ff3d01348e0a2dc369b7efcbac30e4ce86d178 | [log] [tgz] |
|---|---|---|
| author | Dave Liu <daveliu@freescale.com> | Fri Nov 21 16:31:29 2008 +0800 |
| committer | Andrew Fleming-AFLEMING <afleming@freescale.com> | Fri Jan 23 17:03:13 2009 -0600 |
| tree | e3ed66edb226e004cc85cdc4d4a966c55ce4f141 | |
| parent | 80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106 [diff] |
fsl-ddr: clean up the ddr code for DDR3 controller - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>