ARM: k2g: Add ddr3 info
Add ddr3 related info
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c
index dfb27b5..34606f4 100644
--- a/arch/arm/mach-keystone/ddr3.c
+++ b/arch/arm/mach-keystone/ddr3.c
@@ -52,7 +52,8 @@
__raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET);
__raw_writel(phy_cfg->mr0, base + KS2_DDRPHY_MR0_OFFSET);
__raw_writel(phy_cfg->mr1, base + KS2_DDRPHY_MR1_OFFSET);
- __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
+ if (!cpu_is_k2g())
+ __raw_writel(phy_cfg->mr2, base + KS2_DDRPHY_MR2_OFFSET);
__raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
__raw_writel(phy_cfg->pgcr2, base + KS2_DDRPHY_PGCR2_OFFSET);
@@ -64,6 +65,15 @@
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
+ /* Disable ECC for K2G */
+ if (cpu_is_k2g()) {
+ clrbits_le32(base + KS2_DDRPHY_DATX8_4_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_5_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_6_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_7_OFFSET, 0x1);
+ clrbits_le32(base + KS2_DDRPHY_DATX8_8_OFFSET, 0x1);
+ }
+
__raw_writel(phy_cfg->pir_v2, base + KS2_DDRPHY_PIR_OFFSET);
while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1)
;
diff --git a/arch/arm/mach-keystone/include/mach/hardware.h b/arch/arm/mach-keystone/include/mach/hardware.h
index a99713a..2fd5b23 100644
--- a/arch/arm/mach-keystone/include/mach/hardware.h
+++ b/arch/arm/mach-keystone/include/mach/hardware.h
@@ -52,6 +52,10 @@
#define KS2_DDRPHY_ZQ2CR1_OFFSET 0x1A4
#define KS2_DDRPHY_ZQ3CR1_OFFSET 0x1B4
+#define KS2_DDRPHY_DATX8_4_OFFSET 0x2C0
+#define KS2_DDRPHY_DATX8_5_OFFSET 0x300
+#define KS2_DDRPHY_DATX8_6_OFFSET 0x340
+#define KS2_DDRPHY_DATX8_7_OFFSET 0x380
#define KS2_DDRPHY_DATX8_8_OFFSET 0x3C0
#define IODDRM_MASK 0x00000180
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile
index b7c5402..d60496e 100644
--- a/board/ti/ks2_evm/Makefile
+++ b/board/ti/ks2_evm/Makefile
@@ -14,3 +14,4 @@
obj-$(CONFIG_K2L_EVM) += board_k2l.o
obj-$(CONFIG_K2L_EVM) += ddr3_k2l.o
obj-$(CONFIG_K2G_EVM) += board_k2g.o
+obj-$(CONFIG_K2G_EVM) += ddr3_k2g.o
diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c
index bee42bc..7a5509a 100644
--- a/board/ti/ks2_evm/board.c
+++ b/board/ti/ks2_evm/board.c
@@ -43,7 +43,8 @@
gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_MAX_RAM_BANK_SIZE);
aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs);
- ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
+ if (ddr3_size)
+ ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size);
return 0;
}
diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index 2d4602f..81cef70 100644
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -23,7 +23,7 @@
static struct pll_init_data tetris_pll_config = {TETRIS_PLL, 100, 1, 4};
static struct pll_init_data uart_pll_config = {UART_PLL, 64, 1, 4};
static struct pll_init_data nss_pll_config = {NSS_PLL, 250, 3, 2};
-static struct pll_init_data ddr3_pll_config = {DDR3_PLL, 250, 3, 10};
+static struct pll_init_data ddr3_pll_config = {DDR3A_PLL, 250, 3, 10};
struct pll_init_data *get_pll_init_data(int pll)
{
@@ -34,7 +34,7 @@
data = &main_pll_config;
break;
case TETRIS_PLL:
- data = &tetris_pll_config[speed];
+ data = &tetris_pll_config;
break;
case NSS_PLL:
data = &nss_pll_config;
@@ -43,7 +43,7 @@
data = &uart_pll_config;
break;
case DDR3_PLL:
- data = &ddr_pll_config;
+ data = &ddr3_pll_config;
break;
default:
data = NULL;
diff --git a/board/ti/ks2_evm/ddr3_k2g.c b/board/ti/ks2_evm/ddr3_k2g.c
new file mode 100644
index 0000000..344961d
--- /dev/null
+++ b/board/ti/ks2_evm/ddr3_k2g.c
@@ -0,0 +1,64 @@
+/*
+ * K2G: DDR3 initialization
+ *
+ * (C) Copyright 2015
+ * Texas Instruments Incorporated, <www.ti.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include "ddr3_cfg.h"
+#include <asm/arch/ddr3.h>
+
+struct ddr3_phy_config ddr3phy_800_2g = {
+ .pllcr = 0x000DC000ul,
+ .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK),
+ .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)),
+ .ptr0 = 0x42C21590ul,
+ .ptr1 = 0xD05612C0ul,
+ .ptr2 = 0,
+ .ptr3 = 0x06C30D40ul,
+ .ptr4 = 0x06413880ul,
+ .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK),
+ .dcr_val = ((1 << 10)),
+ .dtpr0 = 0x550F6644ul,
+ .dtpr1 = 0x328341E0ul,
+ .dtpr2 = 0x50022A00ul,
+ .mr0 = 0x00001430ul,
+ .mr1 = 0x00000006ul,
+ .mr2 = 0x00000018ul,
+ .dtcr = 0x710035C7ul,
+ .pgcr2 = 0x00F03D09ul,
+ .zq0cr1 = 0x0001005Dul,
+ .zq1cr1 = 0x0001005Bul,
+ .zq2cr1 = 0x0001005Bul,
+ .pir_v1 = 0x00000033ul,
+ .pir_v2 = 0x00000F81ul,
+};
+
+struct ddr3_emif_config ddr3_800_2g = {
+ .sdcfg = 0x62005662ul,
+ .sdtim1 = 0x0A385033ul,
+ .sdtim2 = 0x00001CA5ul,
+ .sdtim3 = 0x21ADFF32ul,
+ .sdtim4 = 0x533F067Ful,
+ .zqcfg = 0x70073200ul,
+ .sdrfc = 0x00000C34ul,
+};
+
+u32 ddr3_init(void)
+{
+ /* Reset DDR3 PHY after PLL enabled */
+ ddr3_reset_ddrphy();
+
+ ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_800_2g);
+ ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_800_2g);
+
+ return 0;
+}
+
+inline int ddr3_get_size(void)
+{
+ return 2;
+}