arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN9130 CRB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN9130 CRB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
diff --git a/arch/arm/dts/cn9130-crb-A.dts b/arch/arm/dts/cn9130-crb-A.dts
new file mode 100644
index 0000000..fa21ef3
--- /dev/null
+++ b/arch/arm/dts/cn9130-crb-A.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Marvell International Ltd.
+ */
+
+#include "cn9130-crb.dtsi"
+
+/ {
+ model = "CN9130-CRB-A";
+ compatible = "marvell,cn9130-crb-A",
+ "marvell,cn9130",
+ "marvell,armada-ap806-quad",
+ "marvell,armada-ap806";
+};
+
+&cp0_comphy {
+ phy0 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy1 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy2 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy3 {
+ phy-type = <PHY_TYPE_PEX0>;
+ };
+
+ phy4 {
+ phy-type = <PHY_TYPE_SFI>;
+ phy-speed = <PHY_SPEED_10_3125G>;
+ };
+
+ phy5 {
+ phy-type = <PHY_TYPE_SGMII2>;
+ phy-speed = <PHY_SPEED_3_125G>;
+ };
+};
+
+&cp0_pcie0 {
+ num-lanes = <4>;
+ /* non-prefetchable memory */
+ ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
+ status = "disabled";
+};
+
+&cp0_usb3_0 {
+ status = "okay";
+};
+
+&cp0_usb3_1 {
+ status = "okay";
+};