Merge tag 'u-boot-imx-20230503' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
u-boot-imx-20230503
-------------------
- Fixes for : pico-imx6ul, smegw01
- new boards: DMSSE20, Reform 2
- fix: get_boot_device, PLL video rate
CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/16211
diff --git a/MAINTAINERS b/MAINTAINERS
index f752132..703b1c2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -291,6 +291,7 @@
F: arch/arm/cpu/armv8/hisilicon
F: arch/arm/include/asm/arch-hi6220/
F: arch/arm/include/asm/arch-hi3660/
+F: arch/arm/mach-histb
ARM HPE GXP ARCHITECTURE
M: Jean-Marie Verdun <verdun@hpe.com>
@@ -1504,7 +1505,9 @@
M: Ilias Apalodimas <ilias.apalodimas@linaro.org>
S: Maintained
T: git https://source.denx.de/u-boot/custodians/u-boot-tpm.git
+F: cmd/tpm*
F: drivers/tpm/
+F: include/tpm*
TQ GROUP
#M: Martin Krause <martin.krause@tq-systems.de>
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index b84c494..99264a6 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -357,7 +357,7 @@
choice
prompt "Select the ARM data write cache policy"
- default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
@@ -578,6 +578,16 @@
help
Support for TI's DaVinci platform.
+config ARCH_HISTB
+ bool "Hisilicon HiSTB SoCs"
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+ select PL01X_SERIAL
+ imply CMD_DM
+ help
+ Support for HiSTB SoCs.
+
config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select ARCH_MISC_INIT
@@ -671,6 +681,25 @@
imply HASH_VERIFY
imply NETDEVICES
+config TARGET_BCMNS
+ bool "Support Broadcom Northstar"
+ select CPU_V7A
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select OF_CONTROL
+ select TIMER
+ select SYS_NS16550
+ select ARM_GLOBAL_TIMER
+ imply SYS_THUMB_BUILD
+ imply MTD_RAW_NAND
+ imply NAND_BRCMNAND
+ imply NAND_BRCMNAND_IPROC
+ help
+ Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
+ ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
+ BCM5301x etc.
+
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
@@ -2155,6 +2184,8 @@
source "arch/arm/mach-highbank/Kconfig"
+source "arch/arm/mach-histb/Kconfig"
+
source "arch/arm/mach-integrator/Kconfig"
source "arch/arm/mach-ipq40xx/Kconfig"
@@ -2266,6 +2297,7 @@
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
+source "board/broadcom/bcmns/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ac602ae..5ebe061 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -61,6 +61,7 @@
machine-$(CONFIG_ARCH_EXYNOS) += exynos
machine-$(CONFIG_ARCH_GXP) += hpe
machine-$(CONFIG_ARCH_HIGHBANK) += highbank
+machine-$(CONFIG_ARCH_HISTB) += histb
machine-$(CONFIG_ARCH_IPQ40XX) += ipq40xx
machine-$(CONFIG_ARCH_K3) += k3
machine-$(CONFIG_ARCH_KEYSTONE) += keystone
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 8a003f4..935b2f1 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1143,9 +1143,6 @@
omap4-sdp.dtb \
omap4-sdp-es23plus.dtb
-dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
- omap5-uevm.dtb
-
dtb-$(CONFIG_TARGET_SAMA7G5EK) += \
at91-sama7g5ek.dtb
@@ -1201,6 +1198,8 @@
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
+dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb
+
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
@@ -1309,6 +1308,8 @@
mt7981-rfb.dtb \
mt7981-emmc-rfb.dtb \
mt7981-sd-rfb.dtb \
+ mt7986a-bpi-r3-sd.dtb \
+ mt7986a-bpi-r3-emmc.dtb \
mt7986a-rfb.dtb \
mt7986b-rfb.dtb \
mt7986a-sd-rfb.dtb \
diff --git a/arch/arm/dts/bcm5301x.dtsi b/arch/arm/dts/bcm5301x.dtsi
new file mode 100644
index 0000000..5fc1b84
--- /dev/null
+++ b/arch/arm/dts/bcm5301x.dtsi
@@ -0,0 +1,581 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
+ *
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <dt-bindings/clock/bcm-nsp.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ chipcommon-a-bus@18000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@300 {
+ compatible = "ns16550";
+ reg = <0x0300 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ status = "disabled";
+ };
+
+ uart1: serial@400 {
+ compatible = "ns16550";
+ reg = <0x0400 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_uart1>;
+ status = "disabled";
+ };
+ };
+
+ mpcore-bus@19000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x19000000 0x00023000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x00000 0x1000>;
+ };
+
+ scu@20000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x20000 0x100>;
+ };
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&periph_clk>;
+ };
+
+ timer@20600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ watchdog@20620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x20620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ gic: interrupt-controller@21000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: cache-controller@22000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ arm,shared-override;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ cache-level = <2>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts =
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ };
+
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x000fffff 0xffff>;
+ interrupt-map =
+ /* ChipCommon */
+ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Switch Register Access Block */
+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 0 */
+ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 1 */
+ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 2 */
+ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 2.0 Controller */
+ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 3.0 Controller */
+ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 0 */
+ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 1 */
+ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 2 */
+ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 3 */
+ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* NAND Controller */
+ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+
+ chipcommon: chipcommon@0 {
+ reg = <0x00000000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcie0: pcie@12000 {
+ reg = <0x00012000 0x1000>;
+ };
+
+ pcie1: pcie@13000 {
+ reg = <0x00013000 0x1000>;
+ };
+
+ pcie2: pcie@14000 {
+ reg = <0x00014000 0x1000>;
+ };
+
+ usb2: usb2@21000 {
+ reg = <0x00021000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&gic>;
+
+ ehci: usb@21000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ehci";
+ reg = <0x00021000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ehci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ehci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+
+ ohci: usb@22000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ohci";
+ reg = <0x00022000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ohci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ohci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3: usb3@23000 {
+ reg = <0x00023000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&gic>;
+
+ xhci: usb@23000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-xhci";
+ reg = <0x00023000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xhci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ gmac0: ethernet@24000 {
+ reg = <0x24000 0x800>;
+ };
+
+ gmac1: ethernet@25000 {
+ reg = <0x25000 0x800>;
+ };
+
+ gmac2: ethernet@26000 {
+ reg = <0x26000 0x800>;
+ };
+
+ gmac3: ethernet@27000 {
+ reg = <0x27000 0x800>;
+ };
+ };
+
+ pwm: pwm@18002000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18002000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ mdio: mdio@18003000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18003000 0x8>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+ };
+
+ mdio-mux@18003000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x18003000 0x4>;
+ mux-mask = <0x200>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,ns-ax-usb3-phy";
+ reg = <0x10>;
+ usb3-dmp-syscon = <&usb3_dmp>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb3_dmp: syscon@18105000 {
+ reg = <0x18105000 0x1000>;
+ };
+
+ uart2: serial@18008000 {
+ compatible = "ns16550a";
+ reg = <0x18008000 0x20>;
+ clocks = <&iprocslow>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@18009000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x18009000 0x50>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ dmu-bus@1800c000 {
+ compatible = "simple-bus";
+ ranges = <0 0x1800c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cru-bus@100 {
+ compatible = "brcm,ns-cru", "simple-mfd";
+ reg = <0x100 0x1a4>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lcpll0: clock-controller@100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";
+ reg = <0x100 0x14>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "pcie_phy",
+ "sdio", "ddr_phy";
+ };
+
+ genpll: clock-controller@140 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-genpll";
+ reg = <0x140 0x24>;
+ clocks = <&osc>;
+ clock-output-names = "genpll", "phy",
+ "ethernetclk",
+ "usbclk", "iprocfast",
+ "sata1", "sata2";
+ };
+
+ usb2_phy: phy@164 {
+ compatible = "brcm,ns-usb2-phy";
+ reg = <0x164 0x4>;
+ brcm,syscon-clkset = <&cru_clkset>;
+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
+ clock-names = "phy-ref-clk";
+ #phy-cells = <0>;
+ };
+
+ cru_clkset: syscon@180 {
+ compatible = "brcm,cru-clkset", "syscon";
+ reg = <0x180 0x4>;
+ };
+
+ pinctrl: pinctrl@1c0 {
+ compatible = "brcm,bcm4708-pinmux";
+ reg = <0x1c0 0x24>;
+ reg-names = "cru_gpio_control";
+
+ spi-pins {
+ groups = "spi_grp";
+ function = "spi";
+ };
+
+ pinmux_i2c: i2c-pins {
+ groups = "i2c_grp";
+ function = "i2c";
+ };
+
+ pinmux_pwm: pwm-pins {
+ groups = "pwm0_grp", "pwm1_grp",
+ "pwm2_grp", "pwm3_grp";
+ function = "pwm";
+ };
+
+ pinmux_uart1: uart1-pins {
+ groups = "uart1_grp";
+ function = "uart1";
+ };
+ };
+
+ thermal: thermal@2c0 {
+ compatible = "brcm,ns-thermal";
+ reg = <0x2c0 0x10>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+ };
+
+ srab: ethernet-switch@18007000 {
+ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
+ reg = <0x18007000 0x1000>;
+
+ status = "disabled";
+
+ /* ports are defined in board DTS */
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ rng: rng@18004000 {
+ compatible = "brcm,bcm5301x-rng";
+ reg = <0x18004000 0x14>;
+ };
+
+ nand_controller: nand-controller@18028000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
+
+ spi@18029200 {
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x18029200 0x184>,
+ <0x18029000 0x124>,
+ <0x1811b408 0x004>,
+ <0x180293a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread";
+ clocks = <&iprocmed>;
+ clock-names = "iprocmed";
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi_nor: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ status = "disabled";
+
+ partitions {
+ compatible = "brcm,bcm947xx-cfe-partitions";
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ coefficients = <(-556) 418000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
index 1722dce..b4f057a 100644
--- a/arch/arm/dts/dragonboard845c.dts
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -21,7 +21,7 @@
};
aliases {
- serial0 = &debug_uart;
+ serial0 = &uart9;
};
memory {
diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
new file mode 100644
index 0000000..eb32076
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "hi3798mv200-u-boot.dtsi"
+
+/* The clock driver is missing */
+&sd0 {
+ status = "disabled";
+};
diff --git a/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
new file mode 100644
index 0000000..c4ca5ed
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-hc2910-2aghd05.dts
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for Skyworth HC2910 with board label 2AGHD05 set-top box.
+ *
+ * Released under the GPLv2 only.
+ */
+
+/dts-v1/;
+
+#include "hi3798mv200.dtsi"
+
+/ {
+ // Usually known as Henan Guangdian HC2910
+ model = "Skyworth HC2910 with board label 2AGHD05";
+ compatible = "skyworth,hc2910-2aghd05", "hisilicon,hi3798mv200";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
+
+&ehci {
+ status = "okay";
+};
+
+&emmc {
+ fifo-depth = <256>;
+ clock-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+ non-removable;
+ bus-width = <8>;
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy-handle = <ð_phy1>;
+ phy-mode = "rgmii";
+ hisilicon,phy-reset-delays-us = <10000 10000 30000>;
+
+ eth_phy1: phy@3 {
+ reg = <3>;
+ };
+};
+
+&ohci {
+ status = "okay";
+};
+
+&sd0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/hi3798mv200-u-boot.dtsi b/arch/arm/dts/hi3798mv200-u-boot.dtsi
new file mode 100644
index 0000000..8917bcf
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200-u-boot.dtsi
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to:
+ * 1) use platform data for the console
+ *
+ */
+
+#include <dt-bindings/reset/ti-syscon.h>
+
+/* The driver in U-Boot does not support "snps,dw-mshc" compatible. */
+&sd0 {
+ compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+&sd1 {
+ compatible = "hisilicon,hi3798mv200-dw-mshc";
+};
+
+/* The clock driver is missing */
+&uart0 {
+ clock = <75000000>;
+};
diff --git a/arch/arm/dts/hi3798mv200.dtsi b/arch/arm/dts/hi3798mv200.dtsi
new file mode 100644
index 0000000..fedf87a
--- /dev/null
+++ b/arch/arm/dts/hi3798mv200.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DTS File for HiSilicon Hi3798mv200 SoC.
+ *
+ * Released under the GPLv2 only.
+ */
+
+#include <dt-bindings/clock/histb-clock.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "hisilicon,hi3798mv200";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ };
+
+ cpu@2 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ };
+
+ cpu@3 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ };
+ };
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
+ <0x0 0xf1002000 0x0 0x100>; /* GICC */
+ #address-cells = <0>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ /* Initialization is done in boot loader */
+ usb2_phy1: hsusb1_phy {
+ compatible = "usb-nop-xceiv";
+ clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
+ clock-names = "main";
+ #phy-cells = <0>;
+ };
+
+ soc: soc@f0000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0xf0000000 0x10000000>;
+
+ crg: clock-reset-controller@8a22000 {
+ compatible = "hisilicon,hi3798mv200-crg", "syscon", "simple-mfd";
+ reg = <0x8a22000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ };
+
+ sysctrl: system-controller@8000000 {
+ compatible = "hisilicon,hi3798mv200-sysctrl", "syscon";
+ reg = <0x8000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <2>;
+ };
+
+ perictrl: peripheral-controller@8a20000 {
+ compatible = "hisilicon,hi3798mv200-perictrl", "syscon",
+ "simple-mfd";
+ reg = <0x8a20000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x8a20000 0x1000>;
+
+ combphy0: phy@850 {
+ compatible = "hisilicon,hi3798mv200-combphy";
+ reg = <0x850 0x8>;
+ #phy-cells = <1>;
+ clocks = <&crg HISTB_COMBPHY0_CLK>;
+ resets = <&crg 0x188 4>;
+ assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
+ assigned-clock-rates = <100000000>;
+ hisilicon,fixed-mode = <PHY_TYPE_USB3>;
+ };
+ };
+
+ pmx0: pinconf@8a21000 {
+ compatible = "pinconf-single";
+ reg = <0x8a21000 0x180>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <7>;
+ };
+
+ uart0: serial@8b00000 {
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0x8b00000 0x1000>;
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sysctrl HISTB_UART0_CLK>;
+ clock-names = "apb_pclk";
+ status = "disabled";
+ };
+
+ sd0: mmc@9820000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x9820000 0x10000>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_SDIO0_CIU_CLK>,
+ <&crg HISTB_SDIO0_BIU_CLK>;
+ clock-names = "ciu", "biu";
+ resets = <&crg 0x9c 4>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ emmc: mmc@9830000 {
+ compatible = "hisilicon,hi3798mv200-dw-mshc";
+ reg = <0x9830000 0x10000>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_MMC_CIU_CLK>,
+ <&crg HISTB_MMC_BIU_CLK>,
+ <&crg HISTB_MMC_SAMPLE_CLK>,
+ <&crg HISTB_MMC_DRV_CLK>;
+ clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
+ resets = <&crg 0xa0 4>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ gmac: ethernet@9840000 {
+ compatible = "hisilicon,hi3798mv200-gmac", "hisilicon,hisi-gmac-v2";
+ reg = <0x9840000 0x1000>,
+ <0x984300c 0x4>;
+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_ETH0_MAC_CLK>,
+ <&crg HISTB_ETH0_MACIF_CLK>;
+ clock-names = "mac_core", "mac_ifc";
+ resets = <&crg 0xcc 0>,
+ <&crg 0xcc 2>,
+ <&crg 0xcc 5>;
+ reset-names = "mac_core", "mac_ifc", "phy";
+ status = "disabled";
+ };
+
+ ohci: ohci@9880000 {
+ compatible = "generic-ohci";
+ reg = <0x9880000 0x10000>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_USB2_BUS_CLK>,
+ <&crg HISTB_USB2_12M_CLK>,
+ <&crg HISTB_USB2_48M_CLK>;
+ clock-names = "bus", "clk12", "clk48";
+ resets = <&crg 0xb8 12>;
+ reset-names = "bus";
+ status = "disabled";
+ };
+
+ ehci: ehci@9890000 {
+ compatible = "generic-ehci";
+ reg = <0x9890000 0x10000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_USB2_BUS_CLK>,
+ <&crg HISTB_USB2_PHY_CLK>,
+ <&crg HISTB_USB2_UTMI_CLK>;
+ clock-names = "bus", "phy", "utmi";
+ resets = <&crg 0xb8 12>,
+ <&crg 0xb8 16>,
+ <&crg 0xb8 13>;
+ reset-names = "bus", "phy", "utmi";
+ phys = <&usb2_phy1>;
+ phy-names = "usb";
+ status = "disabled";
+ };
+
+ sd1: mmc@9c40000 {
+ compatible = "snps,dw-mshc";
+ reg = <0x9c40000 0x10000>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg HISTB_SDIO1_CIU_CLK>,
+ <&crg HISTB_SDIO1_BIU_CLK>;
+ clock-names = "ciu", "biu";
+ resets = <&crg 0x28c 4>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/mt7986a-bpi-r3-emmc.dts b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts
new file mode 100644
index 0000000..4e2e526
--- /dev/null
+++ b/arch/arm/dts/mt7986a-bpi-r3-emmc.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7986a-bpi-r3-sd.dts"
+#include <dt-bindings/gpio/gpio.h>
+/ {
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
diff --git a/arch/arm/dts/mt7986a-bpi-r3-sd.dts b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
new file mode 100644
index 0000000..4d12440
--- /dev/null
+++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7986.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "BananaPi BPi-R3";
+ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb";
+
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+
+ factory {
+ label = "reset";
+ gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
+ };
+
+ wps {
+ label = "wps";
+ gpios = <&gpio 10 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_status_green: green {
+ label = "green:status";
+ gpios = <&gpio 69 GPIO_ACTIVE_HIGH>;
+ };
+
+ led_status_blue: blue {
+ label = "blue:status";
+ gpios = <&gpio 86 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+ð {
+ status = "okay";
+ mediatek,gmac-id = <0>;
+ phy-mode = "sgmii";
+ mediatek,switch = "mt7531";
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&pinctrl {
+ spic_pins: spi1-pins-func-1 {
+ mux {
+ function = "spi";
+ groups = "spi1_2";
+ };
+ };
+
+ uart1_pins: spi1-pins-func-3 {
+ mux {
+ function = "uart";
+ groups = "uart1_2";
+ };
+ };
+
+ pwm_pins: pwm0-pins-func-1 {
+ mux {
+ function = "pwm";
+ groups = "pwm0";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "flash";
+ groups = "emmc_51";
+ };
+
+ conf-cmd-dat {
+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
+ input-enable;
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+
+ conf-clk {
+ pins = "EMMC_CK";
+ drive-strength = <MTK_DRIVE_6mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ conf-dsl {
+ pins = "EMMC_DSL";
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
+ };
+
+ conf-rst {
+ pins = "EMMC_RSTB";
+ drive-strength = <MTK_DRIVE_4mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ spi_flash_pins: spi0-pins-func-1 {
+ mux {
+ function = "flash";
+ groups = "spi0", "spi0_wp_hold";
+ };
+
+ conf-pu {
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
+ };
+
+ conf-pd {
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
+ drive-strength = <MTK_DRIVE_8mA>;
+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
+ };
+ };
+};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm_pins>;
+ status = "okay";
+};
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi_flash_pins>;
+ status = "okay";
+ must_tx;
+ enhance_timing;
+ dma_ext;
+ ipm_design;
+ support_quad;
+ tick_dly = <1>;
+ sample_sel = <0>;
+
+ spi_nor@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <52000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x40000>;
+ };
+
+ partition@40000 {
+ label = "u-boot-env";
+ reg = <0x40000 0x40000>;
+ };
+
+ partition@80000 {
+ label = "reserved";
+ reg = <0x80000 0x80000>;
+ };
+
+ partition@100000 {
+ label = "fip";
+ reg = <0x100000 0x80000>;
+ };
+
+ partition@180000 {
+ label = "recovery";
+ reg = <0x180000 0xa80000>;
+ };
+
+ partition@c00000 {
+ label = "fit";
+ reg = <0xc00000 0x1400000>;
+ };
+ };
+ };
+
+ spi_nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <52000000>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "bl2";
+ reg = <0x0 0x80000>;
+ };
+
+ partition@80000 {
+ label = "factory";
+ reg = <0x80000 0x300000>;
+ };
+
+ partition@380000 {
+ label = "fip";
+ reg = <0x380000 0x200000>;
+ };
+
+ partition@580000 {
+ label = "ubi";
+ reg = <0x580000 0x7a80000>;
+ };
+ };
+ };
+};
+
+&watchdog {
+ status = "disabled";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ bus-width = <4>;
+ max-frequency = <52000000>;
+ cap-sd-highspeed;
+ r_smpl = <1>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ns-board.dts b/arch/arm/dts/ns-board.dts
new file mode 100644
index 0000000..bc2a0dd
--- /dev/null
+++ b/arch/arm/dts/ns-board.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "bcm5301x.dtsi"
+
+/ {
+ /*
+ * The Northstar does not have a proper fallback compatible, but
+ * these basic chips will suffice.
+ */
+ model = "Northstar model";
+ compatible = "brcm,bcm47094", "brcm,bcm4708";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ nand-controller@18028000 {
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Same as using the bcm5301x-nand-cs0-bch1.dtsi
+ * include from the Linux kernel.
+ */
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <1>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "brcm,bcm947xx-cfe-partitions";
+ };
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <125000000>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/omap5-board-common.dtsi b/arch/arm/dts/omap5-board-common.dtsi
deleted file mode 100644
index 45435bb..0000000
--- a/arch/arm/dts/omap5-board-common.dtsi
+++ /dev/null
@@ -1,762 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include "omap5.dtsi"
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
- aliases {
- display0 = &hdmi0;
- };
-
- chosen {
- stdout-path = &uart3;
- };
-
- vmain: fixedregulator-vmain {
- compatible = "regulator-fixed";
- regulator-name = "vmain";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vsys_cobra: fixedregulator-vsys_cobra {
- compatible = "regulator-fixed";
- regulator-name = "vsys_cobra";
- vin-supply = <&vmain>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- vdds_1v8_main: fixedregulator-vdds_1v8_main {
- compatible = "regulator-fixed";
- regulator-name = "vdds_1v8_main";
- vin-supply = <&smps7_reg>;
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vmmcsd_fixed: fixedregulator-mmcsd {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsd_fixed";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- };
-
- mmc3_pwrseq: sdhci0_pwrseq {
- compatible = "mmc-pwrseq-simple";
- clocks = <&clk32kgaudio>;
- clock-names = "ext_clock";
- };
-
- vmmcsdio_fixed: fixedregulator-mmcsdio {
- compatible = "regulator-fixed";
- regulator-name = "vmmcsdio_fixed";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
- enable-active-high;
- startup-delay-us = <70000>;
- pinctrl-names = "default";
- pinctrl-0 = <&wlan_pins>;
- };
-
- /* HS USB Host PHY on PORT 2 */
- hsusb2_phy: hsusb2_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
- clocks = <&auxclk1_ck>;
- clock-names = "main_clk";
- clock-frequency = <19200000>;
- #phy-cells = <0>;
- };
-
- /* HS USB Host PHY on PORT 3 */
- hsusb3_phy: hsusb3_phy {
- compatible = "usb-nop-xceiv";
- reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
- #phy-cells = <0>;
- };
-
- tpd12s015: encoder {
- compatible = "ti,tpd12s015";
-
- pinctrl-names = "default";
- pinctrl-0 = <&tpd12s015_pins>;
-
- /* gpios defined in the board specific dts */
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
-
- tpd12s015_in: endpoint {
- remote-endpoint = <&hdmi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- tpd12s015_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
- };
- };
-
- hdmi0: connector {
- compatible = "hdmi-connector";
- label = "hdmi";
-
- type = "b";
-
- port {
- hdmi_connector_in: endpoint {
- remote-endpoint = <&tpd12s015_out>;
- };
- };
- };
-
- sound: sound {
- compatible = "ti,abe-twl6040";
- ti,model = "omap5-uevm";
-
- ti,jack-detection;
- ti,mclk-freq = <19200000>;
-
- ti,mcpdm = <&mcpdm>;
-
- ti,twl6040 = <&twl6040>;
-
- /* Audio routing */
- ti,audio-routing =
- "Headset Stereophone", "HSOL",
- "Headset Stereophone", "HSOR",
- "Line Out", "AUXL",
- "Line Out", "AUXR",
- "HSMIC", "Headset Mic",
- "Headset Mic", "Headset Mic Bias",
- "AFML", "Line In",
- "AFMR", "Line In";
- };
-};
-
-&gpio8 {
- /* TI trees use GPIO instead of msecure, see also muxing */
- msecure-hog {
- gpio-hog;
- gpios = <10 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "gpio8_234/msecure";
- };
-};
-
-&omap5_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <
- &usbhost_pins
- &led_gpio_pins
- >;
-
- twl6040_pins: pinmux_twl6040_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
- >;
- };
-
- mcpdm_pins: pinmux_mcpdm_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
- OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
- OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
- OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
- OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
- >;
- };
-
- mcbsp1_pins: pinmux_mcbsp1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
- OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
- OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
- OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
- >;
- };
-
- mcbsp2_pins: pinmux_mcbsp2_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
- OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
- OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
- OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
- >;
- };
-
- i2c1_pins: pinmux_i2c1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
- OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
- >;
- };
-
- mcspi2_pins: pinmux_mcspi2_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
- OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
- OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
- OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
- >;
- };
-
- mcspi3_pins: pinmux_mcspi3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
- OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
- OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
- OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
- >;
- };
-
- mmc3_pins: pinmux_mmc3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
- OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
- OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
- OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
- OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
- OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
- >;
- };
-
- wlan_pins: pinmux_wlan_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
- >;
- };
-
- /* TI trees use GPIO mode; msecure mode does not work reliably? */
- palmas_msecure_pins: palmas_msecure_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
- >;
- };
-
- usbhost_pins: pinmux_usbhost_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
- OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
-
- OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
- OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
-
- OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
- OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
- >;
- };
-
- led_gpio_pins: pinmux_led_gpio_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
- >;
- };
-
- uart1_pins: pinmux_uart1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
- OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
- OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
- OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
- >;
- };
-
- uart3_pins: pinmux_uart3_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
- OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
- >;
- };
-
- uart5_pins: pinmux_uart5_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
- OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
- OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
- OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
- >;
- };
-
- dss_hdmi_pins: pinmux_dss_hdmi_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
- OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
- OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
- >;
- };
-
- tpd12s015_pins: pinmux_tpd12s015_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
- >;
- };
-};
-
-&omap5_pmx_wkup {
- pinctrl-names = "default";
- pinctrl-0 = <
- &usbhost_wkup_pins
- >;
-
- palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
- pinctrl-single,pins = <
- /* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
- OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
- >;
- };
-
- usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
- >;
- };
-
- wlcore_irq_pin: pinmux_wlcore_irq_pin {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
- >;
- };
-};
-
-&mmc1 {
- vmmc-supply = <&ldo9_reg>;
- bus-width = <4>;
-};
-
-&mmc2 {
- vmmc-supply = <&vmmcsd_fixed>;
- bus-width = <8>;
- ti,non-removable;
-};
-
-&mmc3 {
- vmmc-supply = <&vmmcsdio_fixed>;
- mmc-pwrseq = <&mmc3_pwrseq>;
- bus-width = <4>;
- non-removable;
- cap-power-off-card;
- pinctrl-names = "default";
- pinctrl-0 = <&mmc3_pins>;
- interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
- &omap5_pmx_core 0x16a>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- wlcore: wlcore@2 {
- compatible = "ti,wl1271";
- reg = <2>;
- pinctrl-names = "default";
- pinctrl-0 = <&wlcore_irq_pin>;
- interrupt-parent = <&gpio1>;
- interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
- ref-clock-frequency = <26000000>;
- };
-};
-
-&mmc4 {
- status = "disabled";
-};
-
-&mmc5 {
- status = "disabled";
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
-
- clock-frequency = <400000>;
-
- palmas: palmas@48 {
- compatible = "ti,palmas";
- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
- reg = <0x48>;
- interrupt-controller;
- #interrupt-cells = <2>;
- ti,system-power-controller;
- ti,mux-pad1 = <0xa1>;
- ti,mux-pad2 = <0x1b>;
- pinctrl-names = "default";
- pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
-
- palmas_gpio: gpio {
- compatible = "ti,palmas-gpio";
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- extcon_usb3: palmas_usb {
- compatible = "ti,palmas-usb-vid";
- ti,enable-vbus-detection;
- ti,enable-id-detection;
- ti,wakeup;
- id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
- };
-
- clk32kgaudio: palmas_clk32k@1 {
- compatible = "ti,palmas-clk32kgaudio";
- #clock-cells = <0>;
- };
-
- rtc {
- compatible = "ti,palmas-rtc";
- interrupt-parent = <&palmas>;
- interrupts = <8 IRQ_TYPE_NONE>;
- ti,backup-battery-chargeable;
- ti,backup-battery-charge-high-current;
- };
-
- gpadc: gpadc {
- compatible = "ti,palmas-gpadc";
- interrupts = <18 0
- 16 0
- 17 0>;
- #io-channel-cells = <1>;
- ti,channel0-current-microamp = <5>;
- ti,channel3-current-microamp = <10>;
- };
-
- palmas_pmic {
- compatible = "ti,palmas-pmic";
- interrupt-parent = <&palmas>;
- interrupts = <14 IRQ_TYPE_NONE>;
- interrupt-names = "short-irq";
-
- ti,ldo6-vibrator;
-
- smps123-in-supply = <&vsys_cobra>;
- smps45-in-supply = <&vsys_cobra>;
- smps6-in-supply = <&vsys_cobra>;
- smps7-in-supply = <&vsys_cobra>;
- smps8-in-supply = <&vsys_cobra>;
- smps9-in-supply = <&vsys_cobra>;
- smps10_out2-in-supply = <&vsys_cobra>;
- smps10_out1-in-supply = <&vsys_cobra>;
- ldo1-in-supply = <&vsys_cobra>;
- ldo2-in-supply = <&vsys_cobra>;
- ldo3-in-supply = <&vdds_1v8_main>;
- ldo4-in-supply = <&vdds_1v8_main>;
- ldo5-in-supply = <&vsys_cobra>;
- ldo6-in-supply = <&vdds_1v8_main>;
- ldo7-in-supply = <&vsys_cobra>;
- ldo8-in-supply = <&vsys_cobra>;
- ldo9-in-supply = <&vmmcsd_fixed>;
- ldoln-in-supply = <&vsys_cobra>;
- ldousb-in-supply = <&vsys_cobra>;
-
- regulators {
- smps123_reg: smps123 {
- /* VDD_OPP_MPU */
- regulator-name = "smps123";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps45_reg: smps45 {
- /* VDD_OPP_MM */
- regulator-name = "smps45";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1310000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps6_reg: smps6 {
- /* VDD_DDR3 - over VDD_SMPS6 */
- regulator-name = "smps6";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps7_reg: smps7 {
- /* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
- regulator-name = "smps7";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps8_reg: smps8 {
- /* VDD_OPP_CORE */
- regulator-name = "smps8";
- regulator-min-microvolt = < 600000>;
- regulator-max-microvolt = <1310000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps9_reg: smps9 {
- /* VDDA_2v1_AUD over VDD_2v1 */
- regulator-name = "smps9";
- regulator-min-microvolt = <2100000>;
- regulator-max-microvolt = <2100000>;
- ti,smps-range = <0x80>;
- };
-
- smps10_out2_reg: smps10_out2 {
- /* VBUS_5V_OTG */
- regulator-name = "smps10_out2";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- smps10_out1_reg: smps10_out1 {
- /* VBUS_5V_OTG */
- regulator-name = "smps10_out1";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- };
-
- ldo1_reg: ldo1 {
- /* VDDAPHY_CAM: vdda_csiport */
- regulator-name = "ldo1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo2_reg: ldo2 {
- /* VCC_2V8_DISP: Does not go anywhere */
- regulator-name = "ldo2";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- /* Unused */
- status = "disabled";
- };
-
- ldo3_reg: ldo3 {
- /* VDDAPHY_MDM: vdda_lli */
- regulator-name = "ldo3";
- regulator-min-microvolt = <1500000>;
- regulator-max-microvolt = <1500000>;
- regulator-boot-on;
- /* Only if Modem is used */
- status = "disabled";
- };
-
- ldo4_reg: ldo4 {
- /* VDDAPHY_DISP: vdda_dsiport/hdmi */
- regulator-name = "ldo4";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- ldo5_reg: ldo5 {
- /* VDDA_1V8_PHY: usb/sata/hdmi.. */
- regulator-name = "ldo5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo6_reg: ldo6 {
- /* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
- regulator-name = "ldo6";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldo7_reg: ldo7 {
- /* VDD_VPP: vpp1 */
- regulator-name = "ldo7";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- /* Only for efuse reprograming! */
- status = "disabled";
- };
-
- ldo8_reg: ldo8 {
- /* VDD_3v0: Does not go anywhere */
- regulator-name = "ldo8";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- /* Unused */
- status = "disabled";
- };
-
- ldo9_reg: ldo9 {
- /* VCC_DV_SDIO: vdds_sdcard */
- regulator-name = "ldo9";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
- regulator-boot-on;
- };
-
- ldoln_reg: ldoln {
- /* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
- regulator-name = "ldoln";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- ldousb_reg: ldousb {
- /* VDDA_3V_USB: VDDA_USBHS33 */
- regulator-name = "ldousb";
- regulator-min-microvolt = <3250000>;
- regulator-max-microvolt = <3250000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- regen3_reg: regen3 {
- /* REGEN3 controls LDO9 supply to card */
- regulator-name = "regen3";
- regulator-always-on;
- regulator-boot-on;
- };
- };
- };
-
- palmas_power_button: palmas_power_button {
- compatible = "ti,palmas-pwrbutton";
- interrupt-parent = <&palmas>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- wakeup-source;
- };
- };
-
- twl6040: twl@4b {
- compatible = "ti,twl6040";
- #clock-cells = <0>;
- reg = <0x4b>;
-
- pinctrl-names = "default";
- pinctrl-0 = <&twl6040_pins>;
-
- /* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
- interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
-
- /* audpwron gpio defined in the board specific dts */
-
- vio-supply = <&smps7_reg>;
- v2v1-supply = <&smps9_reg>;
- enable-active-high;
-
- clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
- clock-names = "clk32k", "mclk";
- };
-};
-
-&mcpdm_module {
- /* Module on the SoC needs external clock from the PMIC */
- pinctrl-names = "default";
- pinctrl-0 = <&mcpdm_pins>;
- status = "okay";
-};
-
-&mcpdm {
- clocks = <&twl6040>;
- clock-names = "pdmclk";
-};
-
-&mcbsp1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp1_pins>;
- status = "okay";
-};
-
-&mcbsp2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcbsp2_pins>;
- status = "okay";
-};
-
-&usbhshost {
- port2-mode = "ehci-hsic";
- port3-mode = "ehci-hsic";
-};
-
-&usbhsehci {
- phys = <0 &hsusb2_phy &hsusb3_phy>;
-};
-
-&usb3 {
- extcon = <&extcon_usb3>;
- vbus-supply = <&smps10_out1_reg>;
-};
-
-&dwc3 {
- extcon = <&extcon_usb3>;
- dr_mode = "otg";
-};
-
-&mcspi1 {
-
-};
-
-&mcspi2 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi2_pins>;
-};
-
-&mcspi3 {
- pinctrl-names = "default";
- pinctrl-0 = <&mcspi3_pins>;
-};
-
-&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
-};
-
-&uart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart3_pins>;
- interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
- <&omap5_pmx_core 0x19c>;
-};
-
-&uart5 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart5_pins>;
-};
-
-&cpu0 {
- cpu0-supply = <&smps123_reg>;
-};
-
-&dss {
- status = "okay";
-};
-
-&hdmi {
- status = "okay";
-
- /* vdda-supply populated in board specific dts file */
-
- pinctrl-names = "default";
- pinctrl-0 = <&dss_hdmi_pins>;
-
- port {
- hdmi_out: endpoint {
- remote-endpoint = <&tpd12s015_in>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-l4-abe.dtsi b/arch/arm/dts/omap5-l4-abe.dtsi
deleted file mode 100644
index f73eea0..0000000
--- a/arch/arm/dts/omap5-l4-abe.dtsi
+++ /dev/null
@@ -1,449 +0,0 @@
-&l4_abe { /* 0x40100000 */
- compatible = "ti,omap5-l4-abe", "simple-bus";
- reg = <0x40100000 0x400>,
- <0x40100400 0x400>;
- reg-names = "la", "ap";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
- <0x49000000 0x49000000 0x100000>;
- segment@0 { /* 0x40100000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges =
- /* CPU to L4 ABE mapping */
- <0x00000000 0x00000000 0x000400>, /* ap 0 */
- <0x00000400 0x00000400 0x000400>, /* ap 1 */
- <0x00022000 0x00022000 0x001000>, /* ap 2 */
- <0x00023000 0x00023000 0x001000>, /* ap 3 */
- <0x00024000 0x00024000 0x001000>, /* ap 4 */
- <0x00025000 0x00025000 0x001000>, /* ap 5 */
- <0x00026000 0x00026000 0x001000>, /* ap 6 */
- <0x00027000 0x00027000 0x001000>, /* ap 7 */
- <0x00028000 0x00028000 0x001000>, /* ap 8 */
- <0x00029000 0x00029000 0x001000>, /* ap 9 */
- <0x0002a000 0x0002a000 0x001000>, /* ap 10 */
- <0x0002b000 0x0002b000 0x001000>, /* ap 11 */
- <0x0002e000 0x0002e000 0x001000>, /* ap 12 */
- <0x0002f000 0x0002f000 0x001000>, /* ap 13 */
- <0x00030000 0x00030000 0x001000>, /* ap 14 */
- <0x00031000 0x00031000 0x001000>, /* ap 15 */
- <0x00032000 0x00032000 0x001000>, /* ap 16 */
- <0x00033000 0x00033000 0x001000>, /* ap 17 */
- <0x00038000 0x00038000 0x001000>, /* ap 18 */
- <0x00039000 0x00039000 0x001000>, /* ap 19 */
- <0x0003a000 0x0003a000 0x001000>, /* ap 20 */
- <0x0003b000 0x0003b000 0x001000>, /* ap 21 */
- <0x0003c000 0x0003c000 0x001000>, /* ap 22 */
- <0x0003d000 0x0003d000 0x001000>, /* ap 23 */
- <0x0003e000 0x0003e000 0x001000>, /* ap 24 */
- <0x0003f000 0x0003f000 0x001000>, /* ap 25 */
- <0x00080000 0x00080000 0x010000>, /* ap 26 */
- <0x00080000 0x00080000 0x001000>, /* ap 27 */
- <0x000a0000 0x000a0000 0x010000>, /* ap 28 */
- <0x000a0000 0x000a0000 0x001000>, /* ap 29 */
- <0x000c0000 0x000c0000 0x010000>, /* ap 30 */
- <0x000c0000 0x000c0000 0x001000>, /* ap 31 */
- <0x000f1000 0x000f1000 0x001000>, /* ap 32 */
- <0x000f2000 0x000f2000 0x001000>, /* ap 33 */
-
- /* L3 to L4 ABE mapping */
- <0x49000000 0x49000000 0x000400>, /* ap 0 */
- <0x49000400 0x49000400 0x000400>, /* ap 1 */
- <0x49022000 0x49022000 0x001000>, /* ap 2 */
- <0x49023000 0x49023000 0x001000>, /* ap 3 */
- <0x49024000 0x49024000 0x001000>, /* ap 4 */
- <0x49025000 0x49025000 0x001000>, /* ap 5 */
- <0x49026000 0x49026000 0x001000>, /* ap 6 */
- <0x49027000 0x49027000 0x001000>, /* ap 7 */
- <0x49028000 0x49028000 0x001000>, /* ap 8 */
- <0x49029000 0x49029000 0x001000>, /* ap 9 */
- <0x4902a000 0x4902a000 0x001000>, /* ap 10 */
- <0x4902b000 0x4902b000 0x001000>, /* ap 11 */
- <0x4902e000 0x4902e000 0x001000>, /* ap 12 */
- <0x4902f000 0x4902f000 0x001000>, /* ap 13 */
- <0x49030000 0x49030000 0x001000>, /* ap 14 */
- <0x49031000 0x49031000 0x001000>, /* ap 15 */
- <0x49032000 0x49032000 0x001000>, /* ap 16 */
- <0x49033000 0x49033000 0x001000>, /* ap 17 */
- <0x49038000 0x49038000 0x001000>, /* ap 18 */
- <0x49039000 0x49039000 0x001000>, /* ap 19 */
- <0x4903a000 0x4903a000 0x001000>, /* ap 20 */
- <0x4903b000 0x4903b000 0x001000>, /* ap 21 */
- <0x4903c000 0x4903c000 0x001000>, /* ap 22 */
- <0x4903d000 0x4903d000 0x001000>, /* ap 23 */
- <0x4903e000 0x4903e000 0x001000>, /* ap 24 */
- <0x4903f000 0x4903f000 0x001000>, /* ap 25 */
- <0x49080000 0x49080000 0x010000>, /* ap 26 */
- <0x49080000 0x49080000 0x001000>, /* ap 27 */
- <0x490a0000 0x490a0000 0x010000>, /* ap 28 */
- <0x490a0000 0x490a0000 0x001000>, /* ap 29 */
- <0x490c0000 0x490c0000 0x010000>, /* ap 30 */
- <0x490c0000 0x490c0000 0x001000>, /* ap 31 */
- <0x490f1000 0x490f1000 0x001000>, /* ap 32 */
- <0x490f2000 0x490f2000 0x001000>; /* ap 33 */
-
- target-module@22000 { /* 0x40122000, ap 2 02.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2208c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x22000 0x1000>,
- <0x49022000 0x49022000 0x1000>;
-
- mcbsp1: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49022000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 33>,
- <&sdma 34>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@24000 { /* 0x40124000, ap 4 04.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2408c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x24000 0x1000>,
- <0x49024000 0x49024000 0x1000>;
-
- mcbsp2: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49024000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 17>,
- <&sdma 18>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@26000 { /* 0x40126000, ap 6 06.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2608c 0x4>;
- reg-names = "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x1000>,
- <0x49026000 0x49026000 0x1000>;
-
- mcbsp3: mcbsp@0 {
- compatible = "ti,omap4-mcbsp";
- reg = <0x0 0xff>, /* MPU private access */
- <0x49026000 0xff>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "common";
- ti,buffer-size = <128>;
- dmas = <&sdma 19>,
- <&sdma 20>;
- dma-names = "tx", "rx";
- status = "disabled";
- };
- };
-
- target-module@28000 { /* 0x40128000, ap 8 08.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x28000 0x1000>,
- <0x49028000 0x49028000 0x1000>;
- };
-
- target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2a000 0x1000>,
- <0x4902a000 0x4902a000 0x1000>;
- };
-
- target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x2e000 0x4>,
- <0x2e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2e000 0x1000>,
- <0x4902e000 0x4902e000 0x1000>;
-
- dmic: dmic@0 {
- compatible = "ti,omap4-dmic";
- reg = <0x0 0x7f>, /* MPU private access */
- <0x4902e000 0x7f>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 67>;
- dma-names = "up_link";
- status = "disabled";
- };
- };
-
- target-module@30000 { /* 0x40130000, ap 14 0e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x30000 0x1000>,
- <0x49030000 0x49030000 0x1000>;
- };
-
- mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x32000 0x4>,
- <0x32010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x32000 0x1000>,
- <0x49032000 0x49032000 0x1000>;
-
- /* Must be only enabled for boards with pdmclk wired */
- status = "disabled";
-
- mcpdm: mcpdm@0 {
- compatible = "ti,omap4-mcpdm";
- reg = <0x0 0x7f>, /* MPU private access */
- <0x49032000 0x7f>; /* L3 Interconnect */
- reg-names = "mpu", "dma";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 65>,
- <&sdma 66>;
- dma-names = "up_link", "dn_link";
- };
- };
-
- target-module@38000 { /* 0x40138000, ap 18 12.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x38000 0x4>,
- <0x38010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x38000 0x1000>,
- <0x49038000 0x49038000 0x1000>;
-
- timer5: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x49038000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3a000 0x4>,
- <0x3a010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3a000 0x1000>,
- <0x4903a000 0x4903a000 0x1000>;
-
- timer6: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903a000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3c000 0x4>,
- <0x3c010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3c000 0x1000>,
- <0x4903c000 0x4903c000 0x1000>;
-
- timer7: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903c000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- };
- };
-
- target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3e000 0x4>,
- <0x3e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3e000 0x1000>,
- <0x4903e000 0x4903e000 0x1000>;
-
- timer8: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>,
- <0x4903e000 0x80>;
- clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-dsp;
- ti,timer-pwm;
- };
- };
-
- target-module@80000 { /* 0x40180000, ap 26 1a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x80000 0x10000>,
- <0x49080000 0x49080000 0x10000>;
- };
-
- target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa0000 0x10000>,
- <0x490a0000 0x490a0000 0x10000>;
- };
-
- target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc0000 0x10000>,
- <0x490c0000 0x490c0000 0x10000>;
- };
-
- target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xf1000 0x4>,
- <0xf1010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
- clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xf1000 0x1000>,
- <0x490f1000 0x490f1000 0x1000>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-l4.dtsi b/arch/arm/dts/omap5-l4.dtsi
deleted file mode 100644
index 4521b64..0000000
--- a/arch/arm/dts/omap5-l4.dtsi
+++ /dev/null
@@ -1,2437 +0,0 @@
-&l4_cfg { /* 0x4a000000 */
- compatible = "ti,omap5-l4-cfg", "simple-bus";
- reg = <0x4a000000 0x800>,
- <0x4a000800 0x800>,
- <0x4a001000 0x1000>;
- reg-names = "ap", "la", "ia0";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4a000000 0x080000>, /* segment 0 */
- <0x00080000 0x4a080000 0x080000>, /* segment 1 */
- <0x00100000 0x4a100000 0x080000>, /* segment 2 */
- <0x00180000 0x4a180000 0x080000>, /* segment 3 */
- <0x00200000 0x4a200000 0x080000>, /* segment 4 */
- <0x00280000 0x4a280000 0x080000>, /* segment 5 */
- <0x00300000 0x4a300000 0x080000>; /* segment 6 */
-
- segment@0 { /* 0x4a000000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x001000>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00002000 0x00002000 0x001000>, /* ap 3 */
- <0x00003000 0x00003000 0x001000>, /* ap 4 */
- <0x00004000 0x00004000 0x001000>, /* ap 5 */
- <0x00005000 0x00005000 0x001000>, /* ap 6 */
- <0x00056000 0x00056000 0x001000>, /* ap 7 */
- <0x00057000 0x00057000 0x001000>, /* ap 8 */
- <0x0005c000 0x0005c000 0x001000>, /* ap 9 */
- <0x00058000 0x00058000 0x001000>, /* ap 10 */
- <0x00062000 0x00062000 0x001000>, /* ap 11 */
- <0x00063000 0x00063000 0x001000>, /* ap 12 */
- <0x00008000 0x00008000 0x002000>, /* ap 21 */
- <0x0000a000 0x0000a000 0x001000>, /* ap 22 */
- <0x00066000 0x00066000 0x001000>, /* ap 23 */
- <0x00067000 0x00067000 0x001000>, /* ap 24 */
- <0x0005e000 0x0005e000 0x002000>, /* ap 69 */
- <0x00060000 0x00060000 0x001000>, /* ap 70 */
- <0x00064000 0x00064000 0x001000>, /* ap 71 */
- <0x00065000 0x00065000 0x001000>, /* ap 72 */
- <0x0005a000 0x0005a000 0x001000>, /* ap 77 */
- <0x0005b000 0x0005b000 0x001000>, /* ap 78 */
- <0x00070000 0x00070000 0x004000>, /* ap 79 */
- <0x00074000 0x00074000 0x001000>, /* ap 80 */
- <0x00075000 0x00075000 0x001000>, /* ap 81 */
- <0x00076000 0x00076000 0x001000>, /* ap 82 */
- <0x00020000 0x00020000 0x020000>, /* ap 109 */
- <0x00040000 0x00040000 0x001000>, /* ap 110 */
- <0x00059000 0x00059000 0x001000>; /* ap 111 */
-
- target-module@2000 { /* 0x4a002000, ap 3 44.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x2000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
-
- scm_core: scm@0 {
- compatible = "ti,omap5-scm-core", "simple-bus";
- reg = <0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x800>;
-
- scm_conf: scm_conf@0 {
- compatible = "syscon";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
-
- scm_padconf_core: scm@800 {
- compatible = "ti,omap5-scm-padconf-core",
- "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x800 0x800>;
-
- omap5_pmx_core: pinmux@40 {
- compatible = "ti,omap5-padconf",
- "pinctrl-single";
- reg = <0x40 0x01b6>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0x7fff>;
- };
-
- omap5_padconf_global: omap5_padconf_global@5a0 {
- compatible = "syscon",
- "simple-bus";
- reg = <0x5a0 0xec>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x5a0 0xec>;
-
- pbias_regulator: pbias_regulator@60 {
- compatible = "ti,pbias-omap5", "ti,pbias-omap";
- reg = <0x60 0x4>;
- syscon = <&omap5_padconf_global>;
- pbias_mmc_reg: pbias_mmc_omap5 {
- regulator-name = "pbias_mmc_omap5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3300000>;
- };
- };
- };
- };
- };
-
- target-module@4000 { /* 0x4a004000, ap 5 5c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x4000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- cm_core_aon: cm_core_aon@0 {
- compatible = "ti,omap5-cm-core-aon",
- "simple-bus";
- reg = <0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000>;
-
- cm_core_aon_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_aon_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@8000 { /* 0x4a008000, ap 21 4c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x8000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x2000>;
-
- cm_core: cm_core@0 {
- compatible = "ti,omap5-cm-core", "simple-bus";
- reg = <0x0 0x2000>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x2000>;
-
- cm_core_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- cm_core_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@20000 { /* 0x4a020000, ap 109 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_otg_ss";
- reg = <0x20000 0x4>,
- <0x20010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_DMADISABLE>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x20000>;
-
- usb3: omap_dwc3@0 {
- compatible = "ti,dwc3";
- reg = <0x0 0x10000>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- utmi-mode = <2>;
- ranges = <0 0 0x20000>;
- dwc3: usb@10000 {
- compatible = "snps,dwc3";
- reg = <0x10000 0x10000>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "peripheral",
- "host",
- "otg";
- phys = <&usb2_phy>, <&usb3_phy>;
- phy-names = "usb2-phy", "usb3-phy";
- dr_mode = "peripheral";
- };
- };
- };
-
- target-module@56000 { /* 0x4a056000, ap 7 02.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x56000 0x4>,
- <0x5602c 0x4>,
- <0x56028 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, dma_clkdm */
- clocks = <&dma_clkctrl OMAP5_DMA_SYSTEM_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x56000 0x1000>;
-
- sdma: dma-controller@0 {
- compatible = "ti,omap4430-sdma", "ti,omap-sdma";
- reg = <0x0 0x1000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
- #dma-cells = <1>;
- dma-channels = <32>;
- dma-requests = <127>;
- };
- };
-
- target-module@58000 { /* 0x4a058000, ap 10 06.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00058000 0x00001000>,
- <0x00001000 0x00059000 0x00001000>,
- <0x00002000 0x0005a000 0x00001000>,
- <0x00003000 0x0005b000 0x00001000>;
- };
-
- target-module@5e000 { /* 0x4a05e000, ap 69 2a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5e000 0x2000>;
- };
-
- target-module@62000 { /* 0x4a062000, ap 11 0e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "usb_tll_hs";
- reg = <0x62000 0x4>,
- <0x62010 0x4>,
- <0x62014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_TLL_HS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x62000 0x1000>;
-
- usbhstll: usbhstll@0 {
- compatible = "ti,usbhs-tll";
- reg = <0x0 0x1000>;
- interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@64000 { /* 0x4a064000, ap 71 1e.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "usb_host_hs";
- reg = <0x64000 0x4>,
- <0x64010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_USB_HOST_HS_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x64000 0x1000>;
-
- usbhshost: usbhshost@0 {
- compatible = "ti,usbhs-host";
- reg = <0x0 0x800>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000>;
- clocks = <&l3init_60m_fclk>,
- <&xclk60mhsp1_ck>,
- <&xclk60mhsp2_ck>;
- clock-names = "refclk_60m_int",
- "refclk_60m_ext_p1",
- "refclk_60m_ext_p2";
-
- usbhsohci: ohci@800 {
- compatible = "ti,ohci-omap3";
- reg = <0x800 0x400>;
- interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
- remote-wakeup-connected;
- };
-
- usbhsehci: ehci@c00 {
- compatible = "ti,ehci-omap";
- reg = <0xc00 0x400>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
- };
-
- target-module@66000 { /* 0x4a066000, ap 23 0a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x66000 0x4>,
- <0x66010 0x4>,
- <0x66014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): mm, dsp_pwrdm, dsp_clkdm */
- clocks = <&dsp_clkctrl OMAP5_MMU_DSP_CLKCTRL 0>;
- clock-names = "fck";
- resets = <&prm_dsp 1>;
- reset-names = "rstctrl";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x66000 0x1000>;
-
- mmu_dsp: mmu@0 {
- compatible = "ti,omap4-iommu";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <0>;
- };
- };
-
- target-module@70000 { /* 0x4a070000, ap 79 2e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x70000 0x4000>;
- };
-
- target-module@75000 { /* 0x4a075000, ap 81 32.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x75000 0x1000>;
- };
- };
-
- segment@80000 { /* 0x4a080000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00059000 0x000d9000 0x001000>, /* ap 13 */
- <0x0005a000 0x000da000 0x001000>, /* ap 14 */
- <0x0005b000 0x000db000 0x001000>, /* ap 15 */
- <0x0005c000 0x000dc000 0x001000>, /* ap 16 */
- <0x0005d000 0x000dd000 0x001000>, /* ap 17 */
- <0x0005e000 0x000de000 0x001000>, /* ap 18 */
- <0x00060000 0x000e0000 0x001000>, /* ap 19 */
- <0x00061000 0x000e1000 0x001000>, /* ap 20 */
- <0x00074000 0x000f4000 0x001000>, /* ap 25 */
- <0x00075000 0x000f5000 0x001000>, /* ap 26 */
- <0x00076000 0x000f6000 0x001000>, /* ap 27 */
- <0x00077000 0x000f7000 0x001000>, /* ap 28 */
- <0x00036000 0x000b6000 0x001000>, /* ap 65 */
- <0x00037000 0x000b7000 0x001000>, /* ap 66 */
- <0x0004d000 0x000cd000 0x001000>, /* ap 67 */
- <0x0004e000 0x000ce000 0x001000>, /* ap 68 */
- <0x00000000 0x00080000 0x004000>, /* ap 83 */
- <0x00004000 0x00084000 0x001000>, /* ap 84 */
- <0x00005000 0x00085000 0x001000>, /* ap 85 */
- <0x00006000 0x00086000 0x001000>, /* ap 86 */
- <0x00007000 0x00087000 0x001000>, /* ap 87 */
- <0x00008000 0x00088000 0x001000>, /* ap 88 */
- <0x00010000 0x00090000 0x004000>, /* ap 89 */
- <0x00014000 0x00094000 0x001000>, /* ap 90 */
- <0x00015000 0x00095000 0x001000>, /* ap 91 */
- <0x00016000 0x00096000 0x001000>, /* ap 92 */
- <0x00017000 0x00097000 0x001000>, /* ap 93 */
- <0x00018000 0x00098000 0x001000>, /* ap 94 */
- <0x00020000 0x000a0000 0x004000>, /* ap 95 */
- <0x00024000 0x000a4000 0x001000>, /* ap 96 */
- <0x00025000 0x000a5000 0x001000>, /* ap 97 */
- <0x00026000 0x000a6000 0x001000>, /* ap 98 */
- <0x00027000 0x000a7000 0x001000>, /* ap 99 */
- <0x00028000 0x000a8000 0x001000>; /* ap 100 */
-
- target-module@0 { /* 0x4a080000, ap 83 28.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x0 0x4>,
- <0x10 0x4>,
- <0x14 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_OCP2SCP1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x00004000>,
- <0x00004000 0x00004000 0x00001000>,
- <0x00005000 0x00005000 0x00001000>,
- <0x00006000 0x00006000 0x00001000>,
- <0x00007000 0x00007000 0x00001000>;
-
- ocp2scp@0 {
- compatible = "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0x20>;
- };
-
- usb2_phy: usb2phy@4000 {
- compatible = "ti,omap-usb2";
- reg = <0x4000 0x7c>;
- syscon-phy-power = <&scm_conf 0x300>;
- clocks = <&usb_phy_cm_clk32k>,
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
- clock-names = "wkupclk", "refclk";
- #phy-cells = <0>;
- };
-
- usb3_phy: usb3phy@4400 {
- compatible = "ti,omap-usb3";
- reg = <0x4400 0x80>,
- <0x4800 0x64>,
- <0x4c00 0x40>;
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- syscon-phy-power = <&scm_conf 0x370>;
- clocks = <&usb_phy_cm_clk32k>,
- <&sys_clkin>,
- <&l3init_clkctrl OMAP5_USB_OTG_SS_CLKCTRL 8>;
- clock-names = "wkupclk",
- "sysclk",
- "refclk";
- #phy-cells = <0>;
- };
- };
-
- target-module@10000 { /* 0x4a090000, ap 89 36.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x10000 0x4>,
- <0x10010 0x4>,
- <0x10014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_OCP2SCP3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00010000 0x00004000>,
- <0x00004000 0x00014000 0x00001000>,
- <0x00005000 0x00015000 0x00001000>,
- <0x00006000 0x00016000 0x00001000>,
- <0x00007000 0x00017000 0x00001000>;
-
- ocp2scp@0 {
- compatible = "ti,omap-ocp2scp";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0 0x20>;
- };
-
- sata_phy: phy@6000 {
- compatible = "ti,phy-pipe3-sata";
- reg = <0x6000 0x80>, /* phy_rx */
- <0x6400 0x64>, /* phy_tx */
- <0x6800 0x40>; /* pll_ctrl */
- reg-names = "phy_rx", "phy_tx", "pll_ctrl";
- syscon-phy-power = <&scm_conf 0x374>;
- clocks = <&sys_clkin>,
- <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
- clock-names = "sysclk", "refclk";
- #phy-cells = <0>;
- };
- };
-
- target-module@20000 { /* 0x4a0a0000, ap 95 50.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00020000 0x00004000>,
- <0x00004000 0x00024000 0x00001000>,
- <0x00005000 0x00025000 0x00001000>,
- <0x00006000 0x00026000 0x00001000>,
- <0x00007000 0x00027000 0x00001000>;
- };
-
- target-module@36000 { /* 0x4a0b6000, ap 65 6c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x36000 0x1000>;
- };
-
- target-module@4d000 { /* 0x4a0cd000, ap 67 64.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4d000 0x1000>;
- };
-
- target-module@59000 { /* 0x4a0d9000, ap 13 20.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x59000 0x1000>;
- };
-
- target-module@5b000 { /* 0x4a0db000, ap 15 10.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5b000 0x1000>;
- };
-
- target-module@5d000 { /* 0x4a0dd000, ap 17 18.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5d000 0x1000>;
- };
-
- target-module@60000 { /* 0x4a0e0000, ap 19 54.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x60000 0x1000>;
- };
-
- target-module@74000 { /* 0x4a0f4000, ap 25 04.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x74000 0x4>,
- <0x74010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
- clocks = <&l4cfg_clkctrl OMAP5_MAILBOX_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x74000 0x1000>;
-
- mailbox: mailbox@0 {
- compatible = "ti,omap4-mailbox";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <3>;
- ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox-ipu {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_dsp: mbox-dsp {
- ti,mbox-tx = <3 0 0>;
- ti,mbox-rx = <2 0 0>;
- };
- };
- };
-
- target-module@76000 { /* 0x4a0f6000, ap 27 0c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x76000 0x4>,
- <0x76010 0x4>,
- <0x76014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4cfg_clkdm */
- clocks = <&l4cfg_clkctrl OMAP5_SPINLOCK_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x76000 0x1000>;
-
- hwspinlock: spinlock@0 {
- compatible = "ti,omap4-hwspinlock";
- reg = <0x0 0x1000>;
- #hwlock-cells = <1>;
- };
- };
- };
-
- segment@100000 { /* 0x4a100000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00002000 0x00102000 0x001000>, /* ap 59 */
- <0x00003000 0x00103000 0x001000>, /* ap 60 */
- <0x00008000 0x00108000 0x001000>, /* ap 61 */
- <0x00009000 0x00109000 0x001000>, /* ap 62 */
- <0x0000a000 0x0010a000 0x001000>, /* ap 63 */
- <0x0000b000 0x0010b000 0x001000>, /* ap 64 */
- <0x00040000 0x00140000 0x010000>, /* ap 101 */
- <0x00050000 0x00150000 0x001000>; /* ap 102 */
-
- target-module@2000 { /* 0x4a102000, ap 59 2c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@8000 { /* 0x4a108000, ap 61 26.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
- };
-
- target-module@a000 { /* 0x4a10a000, ap 63 22.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
- };
-
- target-module@40000 { /* 0x4a140000, ap 101 16.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x40000 0x10000>;
- };
- };
-
- segment@180000 { /* 0x4a180000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- segment@200000 { /* 0x4a200000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0001e000 0x0021e000 0x001000>, /* ap 29 */
- <0x0001f000 0x0021f000 0x001000>, /* ap 30 */
- <0x0000a000 0x0020a000 0x001000>, /* ap 31 */
- <0x0000b000 0x0020b000 0x001000>, /* ap 32 */
- <0x00006000 0x00206000 0x001000>, /* ap 33 */
- <0x00007000 0x00207000 0x001000>, /* ap 34 */
- <0x00004000 0x00204000 0x001000>, /* ap 35 */
- <0x00005000 0x00205000 0x001000>, /* ap 36 */
- <0x00012000 0x00212000 0x001000>, /* ap 37 */
- <0x00013000 0x00213000 0x001000>, /* ap 38 */
- <0x0000c000 0x0020c000 0x001000>, /* ap 39 */
- <0x0000d000 0x0020d000 0x001000>, /* ap 40 */
- <0x00010000 0x00210000 0x001000>, /* ap 41 */
- <0x00011000 0x00211000 0x001000>, /* ap 42 */
- <0x00016000 0x00216000 0x001000>, /* ap 43 */
- <0x00017000 0x00217000 0x001000>, /* ap 44 */
- <0x00014000 0x00214000 0x001000>, /* ap 45 */
- <0x00015000 0x00215000 0x001000>, /* ap 46 */
- <0x00018000 0x00218000 0x001000>, /* ap 47 */
- <0x00019000 0x00219000 0x001000>, /* ap 48 */
- <0x00020000 0x00220000 0x001000>, /* ap 49 */
- <0x00021000 0x00221000 0x001000>, /* ap 50 */
- <0x00026000 0x00226000 0x001000>, /* ap 51 */
- <0x00027000 0x00227000 0x001000>, /* ap 52 */
- <0x00028000 0x00228000 0x001000>, /* ap 53 */
- <0x00029000 0x00229000 0x001000>, /* ap 54 */
- <0x0002a000 0x0022a000 0x001000>, /* ap 55 */
- <0x0002b000 0x0022b000 0x001000>, /* ap 56 */
- <0x0001c000 0x0021c000 0x001000>, /* ap 57 */
- <0x0001d000 0x0021d000 0x001000>, /* ap 58 */
- <0x0001a000 0x0021a000 0x001000>, /* ap 73 */
- <0x0001b000 0x0021b000 0x001000>, /* ap 74 */
- <0x00024000 0x00224000 0x001000>, /* ap 75 */
- <0x00025000 0x00225000 0x001000>, /* ap 76 */
- <0x00002000 0x00202000 0x001000>, /* ap 103 */
- <0x00003000 0x00203000 0x001000>, /* ap 104 */
- <0x00008000 0x00208000 0x001000>, /* ap 105 */
- <0x00009000 0x00209000 0x001000>, /* ap 106 */
- <0x00022000 0x00222000 0x001000>, /* ap 107 */
- <0x00023000 0x00223000 0x001000>; /* ap 108 */
-
- target-module@2000 { /* 0x4a202000, ap 103 3c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@4000 { /* 0x4a204000, ap 35 46.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
- };
-
- target-module@6000 { /* 0x4a206000, ap 33 4e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6000 0x1000>;
- };
-
- target-module@8000 { /* 0x4a208000, ap 105 34.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
- };
-
- target-module@a000 { /* 0x4a20a000, ap 31 30.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
- };
-
- target-module@c000 { /* 0x4a20c000, ap 39 14.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
- };
-
- target-module@10000 { /* 0x4a210000, ap 41 56.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x10000 0x1000>;
- };
-
- target-module@12000 { /* 0x4a212000, ap 37 52.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x12000 0x1000>;
- };
-
- target-module@14000 { /* 0x4a214000, ap 45 1c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x14000 0x1000>;
- };
-
- target-module@16000 { /* 0x4a216000, ap 43 42.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x16000 0x1000>;
- };
-
- target-module@18000 { /* 0x4a218000, ap 47 1a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x18000 0x1000>;
- };
-
- target-module@1a000 { /* 0x4a21a000, ap 73 3e.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1a000 0x1000>;
- };
-
- target-module@1c000 { /* 0x4a21c000, ap 57 40.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1c000 0x1000>;
- };
-
- target-module@1e000 { /* 0x4a21e000, ap 29 12.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x1e000 0x1000>;
- };
-
- target-module@20000 { /* 0x4a220000, ap 49 4a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
- };
-
- target-module@22000 { /* 0x4a222000, ap 107 3a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x22000 0x1000>;
- };
-
- target-module@24000 { /* 0x4a224000, ap 75 48.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x24000 0x1000>;
- };
-
- target-module@26000 { /* 0x4a226000, ap 51 24.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x26000 0x1000>;
- };
-
- target-module@28000 { /* 0x4a228000, ap 53 38.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x28000 0x1000>;
- };
-
- target-module@2a000 { /* 0x4a22a000, ap 55 5a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2a000 0x1000>;
- };
- };
-
- segment@280000 { /* 0x4a280000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-
- segment@300000 { /* 0x4a300000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&l4_per { /* 0x48000000 */
- compatible = "ti,omap5-l4-per", "simple-bus";
- reg = <0x48000000 0x800>,
- <0x48000800 0x800>,
- <0x48001000 0x400>,
- <0x48001400 0x400>,
- <0x48001800 0x400>,
- <0x48001c00 0x400>;
- reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x48000000 0x200000>, /* segment 0 */
- <0x00200000 0x48200000 0x200000>; /* segment 1 */
-
- segment@0 { /* 0x48000000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x000400>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00020000 0x00020000 0x001000>, /* ap 3 */
- <0x00021000 0x00021000 0x001000>, /* ap 4 */
- <0x00032000 0x00032000 0x001000>, /* ap 5 */
- <0x00033000 0x00033000 0x001000>, /* ap 6 */
- <0x00034000 0x00034000 0x001000>, /* ap 7 */
- <0x00035000 0x00035000 0x001000>, /* ap 8 */
- <0x00036000 0x00036000 0x001000>, /* ap 9 */
- <0x00037000 0x00037000 0x001000>, /* ap 10 */
- <0x0003e000 0x0003e000 0x001000>, /* ap 11 */
- <0x0003f000 0x0003f000 0x001000>, /* ap 12 */
- <0x00055000 0x00055000 0x001000>, /* ap 13 */
- <0x00056000 0x00056000 0x001000>, /* ap 14 */
- <0x00057000 0x00057000 0x001000>, /* ap 15 */
- <0x00058000 0x00058000 0x001000>, /* ap 16 */
- <0x00059000 0x00059000 0x001000>, /* ap 17 */
- <0x0005a000 0x0005a000 0x001000>, /* ap 18 */
- <0x0005b000 0x0005b000 0x001000>, /* ap 19 */
- <0x0005c000 0x0005c000 0x001000>, /* ap 20 */
- <0x0005d000 0x0005d000 0x001000>, /* ap 21 */
- <0x0005e000 0x0005e000 0x001000>, /* ap 22 */
- <0x00060000 0x00060000 0x001000>, /* ap 23 */
- <0x0006a000 0x0006a000 0x001000>, /* ap 24 */
- <0x0006b000 0x0006b000 0x001000>, /* ap 25 */
- <0x0006c000 0x0006c000 0x001000>, /* ap 26 */
- <0x0006d000 0x0006d000 0x001000>, /* ap 27 */
- <0x0006e000 0x0006e000 0x001000>, /* ap 28 */
- <0x0006f000 0x0006f000 0x001000>, /* ap 29 */
- <0x00070000 0x00070000 0x001000>, /* ap 30 */
- <0x00071000 0x00071000 0x001000>, /* ap 31 */
- <0x00072000 0x00072000 0x001000>, /* ap 32 */
- <0x00073000 0x00073000 0x001000>, /* ap 33 */
- <0x00061000 0x00061000 0x001000>, /* ap 34 */
- <0x00053000 0x00053000 0x001000>, /* ap 35 */
- <0x00054000 0x00054000 0x001000>, /* ap 36 */
- <0x000b2000 0x000b2000 0x001000>, /* ap 37 */
- <0x000b3000 0x000b3000 0x001000>, /* ap 38 */
- <0x00078000 0x00078000 0x001000>, /* ap 39 */
- <0x00079000 0x00079000 0x001000>, /* ap 40 */
- <0x00086000 0x00086000 0x001000>, /* ap 41 */
- <0x00087000 0x00087000 0x001000>, /* ap 42 */
- <0x00088000 0x00088000 0x001000>, /* ap 43 */
- <0x00089000 0x00089000 0x001000>, /* ap 44 */
- <0x00051000 0x00051000 0x001000>, /* ap 45 */
- <0x00052000 0x00052000 0x001000>, /* ap 46 */
- <0x00098000 0x00098000 0x001000>, /* ap 47 */
- <0x00099000 0x00099000 0x001000>, /* ap 48 */
- <0x0009a000 0x0009a000 0x001000>, /* ap 49 */
- <0x0009b000 0x0009b000 0x001000>, /* ap 50 */
- <0x0009c000 0x0009c000 0x001000>, /* ap 51 */
- <0x0009d000 0x0009d000 0x001000>, /* ap 52 */
- <0x00068000 0x00068000 0x001000>, /* ap 53 */
- <0x00069000 0x00069000 0x001000>, /* ap 54 */
- <0x00090000 0x00090000 0x002000>, /* ap 55 */
- <0x00092000 0x00092000 0x001000>, /* ap 56 */
- <0x000a4000 0x000a4000 0x001000>, /* ap 57 */
- <0x000a6000 0x000a6000 0x001000>, /* ap 58 */
- <0x000a8000 0x000a8000 0x004000>, /* ap 59 */
- <0x000ac000 0x000ac000 0x001000>, /* ap 60 */
- <0x000ad000 0x000ad000 0x001000>, /* ap 61 */
- <0x000ae000 0x000ae000 0x001000>, /* ap 62 */
- <0x00066000 0x00066000 0x001000>, /* ap 63 */
- <0x00067000 0x00067000 0x001000>, /* ap 64 */
- <0x000b4000 0x000b4000 0x001000>, /* ap 65 */
- <0x000b5000 0x000b5000 0x001000>, /* ap 66 */
- <0x000b8000 0x000b8000 0x001000>, /* ap 67 */
- <0x000b9000 0x000b9000 0x001000>, /* ap 68 */
- <0x000ba000 0x000ba000 0x001000>, /* ap 69 */
- <0x000bb000 0x000bb000 0x001000>, /* ap 70 */
- <0x000d1000 0x000d1000 0x001000>, /* ap 71 */
- <0x000d2000 0x000d2000 0x001000>, /* ap 72 */
- <0x000d5000 0x000d5000 0x001000>, /* ap 73 */
- <0x000d6000 0x000d6000 0x001000>, /* ap 74 */
- <0x000a2000 0x000a2000 0x001000>, /* ap 75 */
- <0x000a3000 0x000a3000 0x001000>, /* ap 76 */
- <0x00001400 0x00001400 0x000400>, /* ap 77 */
- <0x00001800 0x00001800 0x000400>, /* ap 78 */
- <0x00001c00 0x00001c00 0x000400>, /* ap 79 */
- <0x000a5000 0x000a5000 0x001000>, /* ap 80 */
- <0x0007a000 0x0007a000 0x001000>, /* ap 81 */
- <0x0007b000 0x0007b000 0x001000>, /* ap 82 */
- <0x0007c000 0x0007c000 0x001000>, /* ap 83 */
- <0x0007d000 0x0007d000 0x001000>; /* ap 84 */
-
- target-module@20000 { /* 0x48020000, ap 3 04.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x20050 0x4>,
- <0x20054 0x4>,
- <0x20058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x20000 0x1000>;
-
- uart3: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@32000 { /* 0x48032000, ap 5 3e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x32000 0x4>,
- <0x32010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x32000 0x1000>;
-
- timer2: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER2_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@34000 { /* 0x48034000, ap 7 46.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x34000 0x4>,
- <0x34010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x34000 0x1000>;
-
- timer3: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER3_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@36000 { /* 0x48036000, ap 9 4e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x36000 0x4>,
- <0x36010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x36000 0x1000>;
-
- timer4: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER4_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@3e000 { /* 0x4803e000, ap 11 56.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x3e000 0x4>,
- <0x3e010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x3e000 0x1000>;
-
- timer9: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER9_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- target-module@51000 { /* 0x48051000, ap 45 2e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x51000 0x4>,
- <0x51010 0x4>,
- <0x51114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO7_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x51000 0x1000>;
-
- gpio7: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@53000 { /* 0x48053000, ap 35 36.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x53000 0x4>,
- <0x53010 0x4>,
- <0x53114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO8_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x53000 0x1000>;
-
- gpio8: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@55000 { /* 0x48055000, ap 13 0e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x55000 0x4>,
- <0x55010 0x4>,
- <0x55114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO2_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x55000 0x1000>;
-
- gpio2: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@57000 { /* 0x48057000, ap 15 06.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x57000 0x4>,
- <0x57010 0x4>,
- <0x57114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO3_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x57000 0x1000>;
-
- gpio3: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@59000 { /* 0x48059000, ap 17 16.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x59000 0x4>,
- <0x59010 0x4>,
- <0x59114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO4_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x59000 0x1000>;
-
- gpio4: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@5b000 { /* 0x4805b000, ap 19 1e.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5b000 0x4>,
- <0x5b010 0x4>,
- <0x5b114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO5_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5b000 0x1000>;
-
- gpio5: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@5d000 { /* 0x4805d000, ap 21 26.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5d000 0x4>,
- <0x5d010 0x4>,
- <0x5d114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 0>,
- <&l4per_clkctrl OMAP5_GPIO6_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x5d000 0x1000>;
-
- gpio6: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@60000 { /* 0x48060000, ap 23 24.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x60000 0x8>,
- <0x60010 0x8>,
- <0x60090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x60000 0x1000>;
-
- i2c3: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@66000 { /* 0x48066000, ap 63 4c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x66050 0x4>,
- <0x66054 0x4>,
- <0x66058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x66000 0x1000>;
-
- uart5: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@68000 { /* 0x48068000, ap 53 54.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x68050 0x4>,
- <0x68054 0x4>,
- <0x68058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART6_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x68000 0x1000>;
-
- uart6: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6a000 { /* 0x4806a000, ap 24 0a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6a050 0x4>,
- <0x6a054 0x4>,
- <0x6a058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6a000 0x1000>;
-
- uart1: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6c000 { /* 0x4806c000, ap 26 22.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6c050 0x4>,
- <0x6c054 0x4>,
- <0x6c058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6c000 0x1000>;
-
- uart2: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@6e000 { /* 0x4806e000, ap 28 44.1 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x6e050 0x4>,
- <0x6e054 0x4>,
- <0x6e058 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_UART4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6e000 0x1000>;
-
- uart4: serial@0 {
- compatible = "ti,omap4-uart";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
- };
- };
-
- target-module@70000 { /* 0x48070000, ap 30 14.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x70000 0x8>,
- <0x70010 0x8>,
- <0x70090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x70000 0x1000>;
-
- i2c1: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@72000 { /* 0x48072000, ap 32 1c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x72000 0x8>,
- <0x72010 0x8>,
- <0x72090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x72000 0x1000>;
-
- i2c2: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@78000 { /* 0x48078000, ap 39 12.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x78000 0x1000>;
- };
-
- target-module@7a000 { /* 0x4807a000, ap 81 2c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x7a000 0x8>,
- <0x7a010 0x8>,
- <0x7a090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x7a000 0x1000>;
-
- i2c4: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@7c000 { /* 0x4807c000, ap 83 34.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x7c000 0x8>,
- <0x7c010 0x8>,
- <0x7c090 0x8>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_I2C5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x7c000 0x1000>;
-
- i2c5: i2c@0 {
- compatible = "ti,omap4-i2c";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
-
- target-module@86000 { /* 0x48086000, ap 41 5e.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x86000 0x4>,
- <0x86010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x86000 0x1000>;
-
- timer10: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER10_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- target-module@88000 { /* 0x48088000, ap 43 66.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- reg = <0x88000 0x4>,
- <0x88010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x88000 0x1000>;
-
- timer11: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&l4per_clkctrl OMAP5_TIMER11_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-pwm;
- };
- };
-
- rng_target: target-module@90000 { /* 0x48090000, ap 55 1a.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x91fe0 0x4>,
- <0x91fe4 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
- clocks = <&l4sec_clkctrl OMAP5_RNG_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x90000 0x2000>;
-
- rng: rng@0 {
- compatible = "ti,omap4-rng";
- reg = <0x0 0x2000>;
- interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@98000 { /* 0x48098000, ap 47 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x98000 0x4>,
- <0x98010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x98000 0x1000>;
-
- mcspi1: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <4>;
- dmas = <&sdma 35>,
- <&sdma 36>,
- <&sdma 37>,
- <&sdma 38>,
- <&sdma 39>,
- <&sdma 40>,
- <&sdma 41>,
- <&sdma 42>;
- dma-names = "tx0", "rx0", "tx1", "rx1",
- "tx2", "rx2", "tx3", "rx3";
- };
- };
-
- target-module@9a000 { /* 0x4809a000, ap 49 10.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x9a000 0x4>,
- <0x9a010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x9a000 0x1000>;
-
- mcspi2: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 43>,
- <&sdma 44>,
- <&sdma 45>,
- <&sdma 46>;
- dma-names = "tx0", "rx0", "tx1", "rx1";
- };
- };
-
- target-module@9c000 { /* 0x4809c000, ap 51 3a.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x9c000 0x4>,
- <0x9c010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_MMC1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x9c000 0x1000>;
-
- mmc1: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- ti,dual-volt;
- ti,needs-special-reset;
- dmas = <&sdma 61>, <&sdma 62>;
- dma-names = "tx", "rx";
- pbias-supply = <&pbias_mmc_reg>;
- };
- };
-
- target-module@a2000 { /* 0x480a2000, ap 75 02.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa2000 0x1000>;
- };
-
- target-module@a4000 { /* 0x480a4000, ap 57 3c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x000a4000 0x00001000>,
- <0x00001000 0x000a5000 0x00001000>;
- };
-
- target-module@a8000 { /* 0x480a8000, ap 59 2a.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa8000 0x4000>;
- };
-
- target-module@ad000 { /* 0x480ad000, ap 61 20.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xad000 0x4>,
- <0xad010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xad000 0x1000>;
-
- mmc3: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 77>, <&sdma 78>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@b2000 { /* 0x480b2000, ap 37 0c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb2000 0x1000>;
- };
-
- target-module@b4000 { /* 0x480b4000, ap 65 42.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xb4000 0x4>,
- <0xb4010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, l3init_pwrdm, l3init_clkdm */
- clocks = <&l3init_clkctrl OMAP5_MMC2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb4000 0x1000>;
-
- mmc2: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 47>, <&sdma 48>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@b8000 { /* 0x480b8000, ap 67 32.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xb8000 0x4>,
- <0xb8010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI3_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xb8000 0x1000>;
-
- mcspi3: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <2>;
- dmas = <&sdma 15>, <&sdma 16>;
- dma-names = "tx0", "rx0";
- };
- };
-
- target-module@ba000 { /* 0x480ba000, ap 69 18.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xba000 0x4>,
- <0xba010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MCSPI4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xba000 0x1000>;
-
- mcspi4: spi@0 {
- compatible = "ti,omap4-mcspi";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <0>;
- ti,spi-num-cs = <1>;
- dmas = <&sdma 70>, <&sdma 71>;
- dma-names = "tx0", "rx0";
- };
- };
-
- target-module@d1000 { /* 0x480d1000, ap 71 28.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xd1000 0x4>,
- <0xd1010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC4_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xd1000 0x1000>;
-
- mmc4: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 57>, <&sdma 58>;
- dma-names = "tx", "rx";
- };
- };
-
- target-module@d5000 { /* 0x480d5000, ap 73 30.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xd5000 0x4>,
- <0xd5010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): core, core_pwrdm, l4per_clkdm */
- clocks = <&l4per_clkctrl OMAP5_MMC5_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xd5000 0x1000>;
-
- mmc5: mmc@0 {
- compatible = "ti,omap4-hsmmc";
- reg = <0x0 0x400>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
- ti,needs-special-reset;
- dmas = <&sdma 59>, <&sdma 60>;
- dma-names = "tx", "rx";
- };
- };
- };
-
- segment@200000 { /* 0x48200000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- };
-};
-
-&l4_wkup { /* 0x4ae00000 */
- compatible = "ti,omap5-l4-wkup", "simple-bus";
- reg = <0x4ae00000 0x800>,
- <0x4ae00800 0x800>,
- <0x4ae01000 0x1000>;
- reg-names = "ap", "la", "ia0";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x4ae00000 0x010000>, /* segment 0 */
- <0x00010000 0x4ae10000 0x010000>, /* segment 1 */
- <0x00020000 0x4ae20000 0x010000>; /* segment 2 */
-
- segment@0 { /* 0x4ae00000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00000000 0x000800>, /* ap 0 */
- <0x00001000 0x00001000 0x001000>, /* ap 1 */
- <0x00000800 0x00000800 0x000800>, /* ap 2 */
- <0x00006000 0x00006000 0x002000>, /* ap 3 */
- <0x00008000 0x00008000 0x001000>, /* ap 4 */
- <0x0000a000 0x0000a000 0x001000>, /* ap 15 */
- <0x0000b000 0x0000b000 0x001000>, /* ap 16 */
- <0x00004000 0x00004000 0x001000>, /* ap 17 */
- <0x00005000 0x00005000 0x001000>, /* ap 18 */
- <0x0000c000 0x0000c000 0x001000>, /* ap 19 */
- <0x0000d000 0x0000d000 0x001000>; /* ap 20 */
-
- target-module@4000 { /* 0x4ae04000, ap 17 20.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "counter_32k";
- reg = <0x4000 0x4>,
- <0x4010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_COUNTER_32K_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- counter32k: counter@0 {
- compatible = "ti,omap-counter32k";
- reg = <0x0 0x40>;
- };
- };
-
- target-module@6000 { /* 0x4ae06000, ap 3 08.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x6000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x6000 0x2000>;
-
- prm: prm@0 {
- compatible = "ti,omap5-prm", "simple-bus";
- reg = <0x0 0x2000>;
- interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x2000>;
-
- prm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- prm_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@a000 { /* 0x4ae0a000, ap 15 2c.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xa000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xa000 0x1000>;
-
- scrm: scrm@0 {
- compatible = "ti,omap5-scrm";
- reg = <0x0 0x1000>;
-
- scrm_clocks: clocks {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- scrm_clockdomains: clockdomains {
- };
- };
- };
-
- target-module@c000 { /* 0x4ae0c000, ap 19 28.0 */
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0xc000 0x4>;
- reg-names = "rev";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
-
- omap5_pmx_wkup: pinmux@840 {
- compatible = "ti,omap5-padconf",
- "pinctrl-single";
- reg = <0x840 0x003c>;
- #address-cells = <1>;
- #size-cells = <0>;
- #pinctrl-cells = <1>;
- #interrupt-cells = <1>;
- interrupt-controller;
- pinctrl-single,register-width = <16>;
- pinctrl-single,function-mask = <0x7fff>;
- };
-
- omap5_scm_wkup_pad_conf: omap5_scm_wkup_pad_conf@da0 {
- compatible = "ti,omap5-scm-wkup-pad-conf",
- "simple-bus";
- reg = <0xda0 0x60>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x60>;
-
- scm_wkup_pad_conf: scm_conf@0 {
- compatible = "syscon", "simple-bus";
- reg = <0x0 0x60>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x60>;
-
- scm_wkup_pad_conf_clocks: clocks@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- };
- };
- };
- };
- };
-
- segment@10000 { /* 0x4ae10000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00010000 0x001000>, /* ap 5 */
- <0x00001000 0x00011000 0x001000>, /* ap 6 */
- <0x00004000 0x00014000 0x001000>, /* ap 7 */
- <0x00005000 0x00015000 0x001000>, /* ap 8 */
- <0x00008000 0x00018000 0x001000>, /* ap 9 */
- <0x00009000 0x00019000 0x001000>, /* ap 10 */
- <0x0000c000 0x0001c000 0x001000>, /* ap 11 */
- <0x0000d000 0x0001d000 0x001000>; /* ap 12 */
-
- target-module@0 { /* 0x4ae10000, ap 5 10.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x0 0x4>,
- <0x10 0x4>,
- <0x114 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 0>,
- <&wkupaon_clkctrl OMAP5_GPIO1_CLKCTRL 8>;
- clock-names = "fck", "dbclk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x1000>;
-
- gpio1: gpio@0 {
- compatible = "ti,omap4-gpio";
- reg = <0x0 0x200>;
- interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
- ti,gpio-always-on;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- target-module@4000 { /* 0x4ae14000, ap 7 14.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x4000 0x4>,
- <0x4010 0x4>,
- <0x4014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,syss-mask = <1>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_WD_TIMER2_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x4000 0x1000>;
-
- wdt2: wdt@0 {
- compatible = "ti,omap5-wdt", "ti,omap3-wdt";
- reg = <0x0 0x80>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- target-module@8000 { /* 0x4ae18000, ap 9 18.0 */
- compatible = "ti,sysc-omap4-timer", "ti,sysc";
- ti,hwmods = "timer1";
- reg = <0x8000 0x4>,
- <0x8010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
- SYSC_OMAP4_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x8000 0x1000>;
-
- timer1: timer@0 {
- compatible = "ti,omap5430-timer";
- reg = <0x0 0x80>;
- clocks = <&wkupaon_clkctrl OMAP5_TIMER1_CLKCTRL 24>;
- clock-names = "fck";
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- ti,timer-alwon;
- };
- };
-
- target-module@c000 { /* 0x4ae1c000, ap 11 1c.0 */
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0xc000 0x4>,
- <0xc010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
- SYSC_OMAP2_SOFTRESET)>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- /* Domains (V, P, C): wkup, wkupaon_pwrdm, wkupaon_clkdm */
- clocks = <&wkupaon_clkctrl OMAP5_KBD_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0xc000 0x1000>;
-
- keypad: keypad@0 {
- compatible = "ti,omap4-keypad";
- reg = <0x0 0x400>;
- };
- };
- };
-
- segment@20000 { /* 0x4ae20000 */
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00006000 0x00026000 0x001000>, /* ap 13 */
- <0x0000a000 0x0002a000 0x001000>, /* ap 14 */
- <0x00000000 0x00020000 0x001000>, /* ap 21 */
- <0x00001000 0x00021000 0x001000>, /* ap 22 */
- <0x00002000 0x00022000 0x001000>, /* ap 23 */
- <0x00003000 0x00023000 0x001000>, /* ap 24 */
- <0x00007000 0x00027000 0x000400>, /* ap 25 */
- <0x00008000 0x00028000 0x000800>, /* ap 26 */
- <0x00009000 0x00029000 0x000100>, /* ap 27 */
- <0x00008800 0x00028800 0x000200>, /* ap 28 */
- <0x00008a00 0x00028a00 0x000100>; /* ap 29 */
-
- target-module@0 { /* 0x4ae20000, ap 21 04.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x0 0x1000>;
- };
-
- target-module@2000 { /* 0x4ae22000, ap 23 0c.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x0 0x2000 0x1000>;
- };
-
- target-module@6000 { /* 0x4ae26000, ap 13 24.0 */
- compatible = "ti,sysc";
- status = "disabled";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x00000000 0x00006000 0x00001000>,
- <0x00001000 0x00007000 0x00000400>,
- <0x00002000 0x00008000 0x00000800>,
- <0x00002800 0x00008800 0x00000200>,
- <0x00002a00 0x00008a00 0x00000100>,
- <0x00003000 0x00009000 0x00000100>;
- };
- };
-};
diff --git a/arch/arm/dts/omap5-uevm.dts b/arch/arm/dts/omap5-uevm.dts
deleted file mode 100644
index b289b57..0000000
--- a/arch/arm/dts/omap5-uevm.dts
+++ /dev/null
@@ -1,200 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
- */
-/dts-v1/;
-
-#include "omap5-board-common.dtsi"
-
-/ {
- model = "TI OMAP5 uEVM board";
- compatible = "ti,omap5-uevm", "ti,omap5";
-
- memory@80000000 {
- device_type = "memory";
- reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
- };
-
- aliases {
- ethernet = ðernet;
- };
-
- leds {
- compatible = "gpio-leds";
- led1 {
- label = "omap5:blue:usr1";
- gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-
- evm_keys {
- compatible = "gpio-keys";
-
- pinctrl-names = "default";
- pinctrl-0 = <&evm_keys_pins>;
-
- #address-cells = <7>;
- #size-cells = <0>;
-
- btn1 {
- label = "BTN1";
- linux,code = <169>;
- gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
- wakeup-source;
- autorepeat;
- debounce-interval = <50>;
- };
- };
-
- evm_leds {
- compatible = "gpio-leds";
-
- led1 {
- label = "omap5:red:led";
- gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc0";
- default-state = "off";
- };
-
- led2 {
- label = "omap5:green:led";
- gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc1";
- default-state = "off";
- };
-
- led3 {
- label = "omap5:blue:led";
- gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "mmc2";
- default-state = "off";
- };
-
- led4 {
- label = "omap5:green:led1";
- gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led5 {
- label = "omap5:green:led2";
- gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- default-state = "off";
- };
-
- led6 {
- label = "omap5:green:led3";
- gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
-
- led7 {
- label = "omap5:green:led4";
- gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "default-on";
- default-state = "off";
- };
-
- led8 {
- label = "omap5:green:led5";
- gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
- linux,default-trigger = "heartbeat";
- default-state = "off";
- };
- };
-};
-
-&hdmi {
- vdda-supply = <&ldo4_reg>;
-};
-
-&i2c1 {
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- };
-};
-
-&i2c5 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c5_pins>;
-
- clock-frequency = <400000>;
-
- gpio9: gpio@22 {
- compatible = "ti,tca6424";
- reg = <0x22>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-};
-
-&mmc1 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc1_pins>;
-
- cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
-};
-
-&omap5_pmx_core {
- evm_keys_pins: pinmux_evm_keys_gpio_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
- >;
- };
-
- i2c5_pins: pinmux_i2c5_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
- OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
- >;
- };
-
- mmc1_pins: pinmux_mmc1_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
- >;
- };
-};
-
-&tpd12s015 {
- gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
- <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
- <&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
-};
-
-&twl6040 {
- ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
-};
-
-&twl6040_pins {
- pinctrl-single,pins = <
- OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
- >;
-};
-
-&usbhsehci {
- #address-cells = <1>;
- #size-cells = <0>;
-
- hub@2 {
- compatible = "usb424,3503";
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ethernet: ethernet@3 {
- compatible = "usb424,9730";
- reg = <3>;
- };
-};
-
-&wlcore {
- compatible = "ti,wl1837";
-};
diff --git a/arch/arm/dts/omap5.dtsi b/arch/arm/dts/omap5.dtsi
deleted file mode 100644
index 76ab2cb..0000000
--- a/arch/arm/dts/omap5.dtsi
+++ /dev/null
@@ -1,583 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
- *
- * Based on "omap4.dtsi"
- */
-
-#include <dt-bindings/bus/ti-sysc.h>
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/pinctrl/omap.h>
-#include <dt-bindings/clock/omap5.h>
-
-/ {
- #address-cells = <2>;
- #size-cells = <2>;
-
- compatible = "ti,omap5";
- interrupt-parent = <&wakeupgen>;
- chosen { };
-
- aliases {
- i2c0 = &i2c1;
- i2c1 = &i2c2;
- i2c2 = &i2c3;
- i2c3 = &i2c4;
- i2c4 = &i2c5;
- serial0 = &uart1;
- serial1 = &uart2;
- serial2 = &uart3;
- serial3 = &uart4;
- serial4 = &uart5;
- serial5 = &uart6;
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x0>;
-
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1500000 1250000
- >;
-
- clocks = <&dpll_mpu_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
-
- /* cooling options */
- #cooling-cells = <2>; /* min followed by max */
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0x1>;
-
- operating-points = <
- /* kHz uV */
- 1000000 1060000
- 1500000 1250000
- >;
-
- clocks = <&dpll_mpu_ck>;
- clock-names = "cpu";
-
- clock-latency = <300000>; /* From omap-cpufreq driver */
-
- /* cooling options */
- #cooling-cells = <2>; /* min followed by max */
- };
- };
-
- thermal-zones {
- #include "omap4-cpu-thermal.dtsi"
- #include "omap5-gpu-thermal.dtsi"
- #include "omap5-core-thermal.dtsi"
- };
-
- timer {
- compatible = "arm,armv7-timer";
- /* PPI secure/nonsecure IRQ */
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
- interrupt-parent = <&gic>;
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- gic: interrupt-controller@48211000 {
- compatible = "arm,cortex-a15-gic";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0 0x48211000 0 0x1000>,
- <0 0x48212000 0 0x2000>,
- <0 0x48214000 0 0x2000>,
- <0 0x48216000 0 0x2000>;
- interrupt-parent = <&gic>;
- };
-
- wakeupgen: interrupt-controller@48281000 {
- compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
- interrupt-controller;
- #interrupt-cells = <3>;
- reg = <0 0x48281000 0 0x1000>;
- interrupt-parent = <&gic>;
- };
-
- /*
- * The soc node represents the soc top level view. It is used for IPs
- * that are not memory mapped in the MPU view or for the MPU itself.
- */
- soc {
- compatible = "ti,omap-infra";
- mpu {
- compatible = "ti,omap4-mpu";
- ti,hwmods = "mpu";
- sram = <&ocmcram>;
- };
- };
-
- /*
- * XXX: Use a flat representation of the OMAP3 interconnect.
- * The real OMAP interconnect network is quite complex.
- * Since it will not bring real advantage to represent that in DT for
- * the moment, just use a fake OCP bus entry to represent the whole bus
- * hierarchy.
- */
- ocp {
- compatible = "ti,omap5-l3-noc", "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0 0xc0000000>;
- dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
- ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
- reg = <0 0x44000000 0 0x2000>,
- <0 0x44800000 0 0x3000>,
- <0 0x45000000 0 0x4000>;
- interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
-
- l4_wkup: interconnect@4ae00000 {
- };
-
- l4_cfg: interconnect@4a000000 {
- };
-
- l4_per: interconnect@48000000 {
- };
-
- l4_abe: interconnect@40100000 {
- };
-
- ocmcram: sram@40300000 {
- compatible = "mmio-sram";
- reg = <0x40300000 0x20000>; /* 128k */
- };
-
- gpmc: gpmc@50000000 {
- compatible = "ti,omap4430-gpmc";
- reg = <0x50000000 0x1000>;
- #address-cells = <2>;
- #size-cells = <1>;
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- dmas = <&sdma 4>;
- dma-names = "rxtx";
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- ti,hwmods = "gpmc";
- clocks = <&l3_iclk_div>;
- clock-names = "fck";
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- target-module@55082000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x55082000 0x4>,
- <0x55082010 0x4>,
- <0x55082014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
- clock-names = "fck";
- resets = <&prm_core 2>;
- reset-names = "rstctrl";
- ranges = <0x0 0x55082000 0x100>;
- #size-cells = <1>;
- #address-cells = <1>;
-
- mmu_ipu: mmu@0 {
- compatible = "ti,omap4-iommu";
- reg = <0x0 0x100>;
- interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- #iommu-cells = <0>;
- ti,iommu-bus-err-back;
- };
- };
-
- dmm@4e000000 {
- compatible = "ti,omap5-dmm";
- reg = <0x4e000000 0x800>;
- interrupts = <0 113 0x4>;
- ti,hwmods = "dmm";
- };
-
- emif1: emif@4c000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif1";
- ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4c000000 0x400>;
- interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
- hw-caps-temp-alert;
- };
-
- emif2: emif@4d000000 {
- compatible = "ti,emif-4d5";
- ti,hwmods = "emif2";
- ti,no-idle-on-init;
- phy-type = <2>; /* DDR PHY type: Intelli PHY */
- reg = <0x4d000000 0x400>;
- interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
- hw-caps-read-idle-ctrl;
- hw-caps-ll-interface;
- hw-caps-temp-alert;
- };
-
- bandgap: bandgap@4a0021e0 {
- reg = <0x4a0021e0 0xc
- 0x4a00232c 0xc
- 0x4a002380 0x2c
- 0x4a0023C0 0x3c>;
- interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
- compatible = "ti,omap5430-bandgap";
-
- #thermal-sensor-cells = <1>;
- };
-
- /* OCP2SCP3 */
- sata: sata@4a141100 {
- compatible = "snps,dwc-ahci";
- reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
- interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
- phys = <&sata_phy>;
- phy-names = "sata-phy";
- clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
- ti,hwmods = "sata";
- ports-implemented = <0x1>;
- };
-
- target-module@56000000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x5600fe00 0x4>,
- <0x5600fe10 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x56000000 0x2000000>;
-
- /*
- * Closed source PowerVR driver, no child device
- * binding or driver in mainline
- */
- };
-
- target-module@58000000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x58000000 4>,
- <0x58000014 4>;
- reg-names = "rev", "syss";
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
- clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x58000000 0x1000000>;
-
- dss: dss@0 {
- compatible = "ti,omap5-dss";
- reg = <0 0x80>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0 0x1000000>;
-
- target-module@1000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x1000 0x4>,
- <0x1010 0x4>,
- <0x1014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-midle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1000 0x1000>;
-
- dispc@0 {
- compatible = "ti,omap5-dispc";
- reg = <0 0x1000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@2000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x2000 0x4>,
- <0x2010 0x4>,
- <0x2014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x2000 0x1000>;
-
- rfbi: encoder@0 {
- compatible = "ti,omap5-rfbi";
- reg = <0 0x100>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
- clock-names = "fck", "ick";
- };
- };
-
- target-module@5000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x5000 0x4>,
- <0x5010 0x4>,
- <0x5014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x5000 0x1000>;
-
- dsi1: encoder@0 {
- compatible = "ti,omap5-dsi";
- reg = <0 0x200>,
- <0x200 0x40>,
- <0x300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@9000 {
- compatible = "ti,sysc-omap2", "ti,sysc";
- reg = <0x9000 0x4>,
- <0x9010 0x4>,
- <0x9014 0x4>;
- reg-names = "rev", "sysc", "syss";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>;
- ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
- SYSC_OMAP2_ENAWAKEUP |
- SYSC_OMAP2_SOFTRESET |
- SYSC_OMAP2_AUTOIDLE)>;
- ti,syss-mask = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x9000 0x1000>;
-
- dsi2: encoder@0 {
- compatible = "ti,omap5-dsi";
- reg = <0 0x200>,
- <0x200 0x40>,
- <0x300 0x40>;
- reg-names = "proto", "phy", "pll";
- interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck";
- };
- };
-
- target-module@40000 {
- compatible = "ti,sysc-omap4", "ti,sysc";
- reg = <0x40000 0x4>,
- <0x40010 0x4>;
- reg-names = "rev", "sysc";
- ti,sysc-sidle = <SYSC_IDLE_FORCE>,
- <SYSC_IDLE_NO>,
- <SYSC_IDLE_SMART>,
- <SYSC_IDLE_SMART_WKUP>;
- ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
- clock-names = "fck", "dss_clk";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x40000 0x40000>;
-
- hdmi: encoder@0 {
- compatible = "ti,omap5-hdmi";
- reg = <0 0x200>,
- <0x200 0x80>,
- <0x300 0x80>,
- <0x20000 0x19000>;
- reg-names = "wp", "pll", "phy", "core";
- interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
- <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
- clock-names = "fck", "sys_clk";
- dmas = <&sdma 76>;
- dma-names = "audio_tx";
- };
- };
- };
- };
-
- abb_mpu: regulator-abb-mpu {
- compatible = "ti,abb-v2";
- regulator-name = "abb_mpu";
- #address-cells = <0>;
- #size-cells = <0>;
- clocks = <&sys_clkin>;
- ti,settling-time = <50>;
- ti,clock-cycles = <16>;
-
- reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
- <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
- reg-names = "base-address", "int-address",
- "efuse-address", "ldo-address";
- ti,tranxdone-status-mask = <0x80>;
- /* LDOVBBMPU_MUX_CTRL */
- ti,ldovbb-override-mask = <0x400>;
- /* LDOVBBMPU_VSET_OUT */
- ti,ldovbb-vset-mask = <0x1F>;
-
- /*
- * NOTE: only FBB mode used but actual vset will
- * determine final biasing
- */
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1060000 0 0x0 0 0x02000000 0x01F00000
- 1250000 0 0x4 0 0x02000000 0x01F00000
- >;
- };
-
- abb_mm: regulator-abb-mm {
- compatible = "ti,abb-v2";
- regulator-name = "abb_mm";
- #address-cells = <0>;
- #size-cells = <0>;
- clocks = <&sys_clkin>;
- ti,settling-time = <50>;
- ti,clock-cycles = <16>;
-
- reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
- <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
- reg-names = "base-address", "int-address",
- "efuse-address", "ldo-address";
- ti,tranxdone-status-mask = <0x80000000>;
- /* LDOVBBMM_MUX_CTRL */
- ti,ldovbb-override-mask = <0x400>;
- /* LDOVBBMM_VSET_OUT */
- ti,ldovbb-vset-mask = <0x1F>;
-
- /*
- * NOTE: only FBB mode used but actual vset will
- * determine final biasing
- */
- ti,abb_info = <
- /*uV ABB efuse rbb_m fbb_m vset_m*/
- 1025000 0 0x0 0 0x02000000 0x01F00000
- 1120000 0 0x4 0 0x02000000 0x01F00000
- >;
- };
- };
-};
-
-&cpu_thermal {
- polling-delay = <500>; /* milliseconds */
- coefficients = <65 (-1791)>;
-};
-
-#include "omap5-l4.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&gpu_thermal {
- coefficients = <117 (-2992)>;
-};
-
-&core_thermal {
- coefficients = <0 2000>;
-};
-
-#include "omap5-l4-abe.dtsi"
-#include "omap54xx-clocks.dtsi"
-
-&prm {
- prm_dsp: prm@400 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x400 0x100>;
- #reset-cells = <1>;
- };
-
- prm_core: prm@700 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x700 0x100>;
- #reset-cells = <1>;
- };
-
- prm_iva: prm@1200 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x1200 0x100>;
- #reset-cells = <1>;
- };
-
- prm_device: prm@1c00 {
- compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
- reg = <0x1c00 0x100>;
- #reset-cells = <1>;
- };
-};
diff --git a/arch/arm/dts/omap54xx-clocks.dtsi b/arch/arm/dts/omap54xx-clocks.dtsi
deleted file mode 100644
index 4dd3c93..0000000
--- a/arch/arm/dts/omap54xx-clocks.dtsi
+++ /dev/null
@@ -1,1208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Device Tree Source for OMAP5 clock data
- *
- * Copyright (C) 2013 Texas Instruments, Inc.
- */
-&cm_core_aon_clocks {
- pad_clks_src_ck: pad_clks_src_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- pad_clks_ck: pad_clks_ck@108 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_src_ck>;
- ti,bit-shift = <8>;
- reg = <0x0108>;
- };
-
- secure_32k_clk_src_ck: secure_32k_clk_src_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- slimbus_src_clk: slimbus_src_clk {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- slimbus_clk: slimbus_clk@108 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_src_clk>;
- ti,bit-shift = <10>;
- reg = <0x0108>;
- };
-
- sys_32k_ck: sys_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
- virt_12000000_ck: virt_12000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <12000000>;
- };
-
- virt_13000000_ck: virt_13000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <13000000>;
- };
-
- virt_16800000_ck: virt_16800000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <16800000>;
- };
-
- virt_19200000_ck: virt_19200000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <19200000>;
- };
-
- virt_26000000_ck: virt_26000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <26000000>;
- };
-
- virt_27000000_ck: virt_27000000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <27000000>;
- };
-
- virt_38400000_ck: virt_38400000_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <38400000>;
- };
-
- xclk60mhsp1_ck: xclk60mhsp1_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <60000000>;
- };
-
- xclk60mhsp2_ck: xclk60mhsp2_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <60000000>;
- };
-
- dpll_abe_ck: dpll_abe_ck@1e0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-m4xen-clock";
- clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
- reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
- };
-
- dpll_abe_x2_ck: dpll_abe_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_abe_ck>;
- };
-
- dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_x2_ck>;
- ti,max-div = <31>;
- reg = <0x01f0>;
- ti,index-starts-at-one;
- };
-
- abe_24m_fclk: abe_24m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <8>;
- };
-
- abe_clk: abe_clk@108 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- ti,max-div = <4>;
- reg = <0x0108>;
- ti,index-power-of-two;
- };
-
- abe_iclk: abe_iclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&aess_fclk>;
- ti,bit-shift = <24>;
- reg = <0x0528>;
- ti,dividers = <2>, <1>;
- };
-
- abe_lp_clk_div: abe_lp_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_abe_x2_ck>;
- ti,max-div = <31>;
- reg = <0x01f4>;
- ti,index-starts-at-one;
- };
-
- dpll_core_byp_mux: dpll_core_byp_mux@12c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
- ti,bit-shift = <23>;
- reg = <0x012c>;
- };
-
- dpll_core_ck: dpll_core_ck@120 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-core-clock";
- clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
- reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
- };
-
- dpll_core_x2_ck: dpll_core_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_core_ck>;
- };
-
- dpll_core_h21x2_ck: dpll_core_h21x2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- c2c_fclk: c2c_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h21x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- c2c_iclk: c2c_iclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&c2c_fclk>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- dpll_core_h11x2_ck: dpll_core_h11x2_ck@138 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0138>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x013c>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0140>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0144>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0154>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0158>;
- ti,index-starts-at-one;
- };
-
- dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <63>;
- reg = <0x015c>;
- ti,index-starts-at-one;
- };
-
- dpll_core_m2_ck: dpll_core_m2_ck@130 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_ck>;
- ti,max-div = <31>;
- reg = <0x0130>;
- ti,index-starts-at-one;
- };
-
- dpll_core_m3x2_ck: dpll_core_m3x2_ck@134 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_core_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0134>;
- ti,index-starts-at-one;
- };
-
- iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h12x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x01ac>;
- };
-
- dpll_iva_ck: dpll_iva_ck@1a0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
- reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
- assigned-clocks = <&dpll_iva_ck>;
- assigned-clock-rates = <1165000000>;
- };
-
- dpll_iva_x2_ck: dpll_iva_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_iva_ck>;
- };
-
- dpll_iva_h11x2_ck: dpll_iva_h11x2_ck@1b8 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_iva_x2_ck>;
- ti,max-div = <63>;
- reg = <0x01b8>;
- ti,index-starts-at-one;
- assigned-clocks = <&dpll_iva_h11x2_ck>;
- assigned-clock-rates = <465920000>;
- };
-
- dpll_iva_h12x2_ck: dpll_iva_h12x2_ck@1bc {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_iva_x2_ck>;
- ti,max-div = <63>;
- reg = <0x01bc>;
- ti,index-starts-at-one;
- assigned-clocks = <&dpll_iva_h12x2_ck>;
- assigned-clock-rates = <388300000>;
- };
-
- mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_core_h12x2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_mpu_ck: dpll_mpu_ck@160 {
- #clock-cells = <0>;
- compatible = "ti,omap5-mpu-dpll-clock";
- clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
- reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
- };
-
- dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_mpu_ck>;
- ti,max-div = <31>;
- reg = <0x0170>;
- ti,index-starts-at-one;
- };
-
- per_dpll_hs_clk_div: per_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_abe_m3x2_ck>;
- clock-mult = <1>;
- clock-div = <3>;
- };
-
- l3_iclk_div: l3_iclk_div@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- ti,max-div = <2>;
- ti,bit-shift = <4>;
- reg = <0x100>;
- clocks = <&dpll_core_h12x2_ck>;
- ti,index-power-of-two;
- };
-
- gpu_l3_iclk: gpu_l3_iclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&l3_iclk_div>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- l4_root_clk_div: l4_root_clk_div@100 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- ti,max-div = <2>;
- ti,bit-shift = <8>;
- reg = <0x100>;
- clocks = <&l3_iclk_div>;
- ti,index-power-of-two;
- };
-
- slimbus1_slimbus_clk: slimbus1_slimbus_clk@560 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_clk>;
- ti,bit-shift = <11>;
- reg = <0x0560>;
- };
-
- aess_fclk: aess_fclk@528 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&abe_clk>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x0528>;
- };
-
- mcasp_sync_mux_ck: mcasp_sync_mux_ck@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
- ti,bit-shift = <26>;
- reg = <0x0540>;
- };
-
- mcasp_gfclk: mcasp_gfclk@540 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
- ti,bit-shift = <24>;
- reg = <0x0540>;
- };
-
- dummy_ck: dummy_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <0>;
- };
-};
-&prm_clocks {
- sys_clkin: sys_clkin@110 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
- reg = <0x0110>;
- ti,index-starts-at-one;
- };
-
- abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@108 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- reg = <0x0108>;
- };
-
- abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&sys_32k_ck>;
- reg = <0x010c>;
- };
-
- custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_clkin>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- dss_syc_gfclk_div: dss_syc_gfclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&sys_clkin>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&abe_lp_clk_div>;
- reg = <0x0108>;
- };
-
- l3instr_ts_gclk_div: l3instr_ts_gclk_div {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&wkupaon_iclk_mux>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-};
-
-&cm_core_clocks {
-
- dpll_per_byp_mux: dpll_per_byp_mux@14c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x014c>;
- };
-
- dpll_per_ck: dpll_per_ck@140 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
- reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
- };
-
- dpll_per_x2_ck: dpll_per_x2_ck {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-x2-clock";
- clocks = <&dpll_per_ck>;
- };
-
- dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0158>;
- ti,index-starts-at-one;
- };
-
- dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x015c>;
- ti,index-starts-at-one;
- };
-
- dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <63>;
- reg = <0x0164>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m2_ck: dpll_per_m2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_ck>;
- ti,max-div = <31>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0150>;
- ti,index-starts-at-one;
- };
-
- dpll_per_m3x2_ck: dpll_per_m3x2_ck@154 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_x2_ck>;
- ti,max-div = <31>;
- reg = <0x0154>;
- ti,index-starts-at-one;
- };
-
- dpll_unipro1_ck: dpll_unipro1_ck@200 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&sys_clkin>;
- reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
- };
-
- dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_unipro1_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_unipro1_m2_ck: dpll_unipro1_m2_ck@210 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_unipro1_ck>;
- ti,max-div = <127>;
- reg = <0x0210>;
- ti,index-starts-at-one;
- };
-
- dpll_unipro2_ck: dpll_unipro2_ck@1c0 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-clock";
- clocks = <&sys_clkin>, <&sys_clkin>;
- reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
- };
-
- dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_unipro2_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_unipro2_m2_ck: dpll_unipro2_m2_ck@1d0 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_unipro2_ck>;
- ti,max-div = <127>;
- reg = <0x01d0>;
- ti,index-starts-at-one;
- };
-
- dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
- ti,bit-shift = <23>;
- reg = <0x018c>;
- };
-
- dpll_usb_ck: dpll_usb_ck@180 {
- #clock-cells = <0>;
- compatible = "ti,omap4-dpll-j-type-clock";
- clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
- reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
- };
-
- dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_usb_ck>;
- clock-mult = <1>;
- clock-div = <1>;
- };
-
- dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_usb_ck>;
- ti,max-div = <127>;
- reg = <0x0190>;
- ti,index-starts-at-one;
- };
-
- func_128m_clk: func_128m_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_h11x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- func_12m_fclk: func_12m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <16>;
- };
-
- func_24m_clk: func_24m_clk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- func_48m_fclk: func_48m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <4>;
- };
-
- func_96m_fclk: func_96m_fclk {
- #clock-cells = <0>;
- compatible = "fixed-factor-clock";
- clocks = <&dpll_per_m2x2_ck>;
- clock-mult = <1>;
- clock-div = <2>;
- };
-
- l3init_60m_fclk: l3init_60m_fclk@104 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_usb_m2_ck>;
- reg = <0x0104>;
- ti,dividers = <1>, <8>;
- };
-
- iss_ctrlclk: iss_ctrlclk@1320 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&func_96m_fclk>;
- ti,bit-shift = <8>;
- reg = <0x1320>;
- };
-
- lli_txphy_clk: lli_txphy_clk@f20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_unipro1_clkdcoldo>;
- ti,bit-shift = <8>;
- reg = <0x0f20>;
- };
-
- lli_txphy_ls_clk: lli_txphy_ls_clk@f20 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&dpll_unipro1_m2_ck>;
- ti,bit-shift = <9>;
- reg = <0x0f20>;
- };
-
- usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_32k_ck>;
- ti,bit-shift = <8>;
- reg = <0x0640>;
- };
-
- fdif_fclk: fdif_fclk@1328 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_h11x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x1328>;
- };
-
- gpu_core_gclk_mux: gpu_core_gclk_mux@1520 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
- ti,bit-shift = <24>;
- reg = <0x1520>;
- };
-
- gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1520 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
- ti,bit-shift = <25>;
- reg = <0x1520>;
- };
-
- hsi_fclk: hsi_fclk@1638 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_per_m2x2_ck>;
- ti,bit-shift = <24>;
- ti,max-div = <2>;
- reg = <0x1638>;
- };
-};
-
-&cm_core_clockdomains {
- l3init_clkdm: l3init_clkdm {
- compatible = "ti,clockdomain";
- clocks = <&dpll_usb_ck>;
- };
-};
-
-&scrm_clocks {
- auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0310>;
- };
-
- auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0310>;
- };
-
- auxclk0_src_ck: auxclk0_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
- };
-
- auxclk0_ck: auxclk0_ck@310 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk0_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0310>;
- };
-
- auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0314>;
- };
-
- auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0314>;
- };
-
- auxclk1_src_ck: auxclk1_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
- };
-
- auxclk1_ck: auxclk1_ck@314 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk1_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0314>;
- };
-
- auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0318>;
- };
-
- auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0318>;
- };
-
- auxclk2_src_ck: auxclk2_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
- };
-
- auxclk2_ck: auxclk2_ck@318 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk2_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0318>;
- };
-
- auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x031c>;
- };
-
- auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x031c>;
- };
-
- auxclk3_src_ck: auxclk3_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
- };
-
- auxclk3_ck: auxclk3_ck@31c {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk3_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x031c>;
- };
-
- auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,composite-no-wait-gate-clock";
- clocks = <&dpll_core_m3x2_ck>;
- ti,bit-shift = <8>;
- reg = <0x0320>;
- };
-
- auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,composite-mux-clock";
- clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
- ti,bit-shift = <1>;
- reg = <0x0320>;
- };
-
- auxclk4_src_ck: auxclk4_src_ck {
- #clock-cells = <0>;
- compatible = "ti,composite-clock";
- clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
- };
-
- auxclk4_ck: auxclk4_ck@320 {
- #clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&auxclk4_src_ck>;
- ti,bit-shift = <16>;
- ti,max-div = <16>;
- reg = <0x0320>;
- };
-
- auxclkreq0_ck: auxclkreq0_ck@210 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0210>;
- };
-
- auxclkreq1_ck: auxclkreq1_ck@214 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0214>;
- };
-
- auxclkreq2_ck: auxclkreq2_ck@218 {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x0218>;
- };
-
- auxclkreq3_ck: auxclkreq3_ck@21c {
- #clock-cells = <0>;
- compatible = "ti,mux-clock";
- clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
- ti,bit-shift = <2>;
- reg = <0x021c>;
- };
-};
-
-&cm_core_aon {
- mpu_cm: mpu_cm@300 {
- compatible = "ti,omap4-cm";
- reg = <0x300 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x300 0x100>;
-
- mpu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- dsp_cm: dsp_cm@400 {
- compatible = "ti,omap4-cm";
- reg = <0x400 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x400 0x100>;
-
- dsp_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- abe_cm: abe_cm@500 {
- compatible = "ti,omap4-cm";
- reg = <0x500 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x500 0x100>;
-
- abe_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x64>;
- #clock-cells = <2>;
- };
- };
-
-};
-
-&cm_core {
- l3main1_cm: l3main1_cm@700 {
- compatible = "ti,omap4-cm";
- reg = <0x700 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x700 0x100>;
-
- l3main1_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- l3main2_cm: l3main2_cm@800 {
- compatible = "ti,omap4-cm";
- reg = <0x800 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x800 0x100>;
-
- l3main2_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- ipu_cm: ipu_cm@900 {
- compatible = "ti,omap4-cm";
- reg = <0x900 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x900 0x100>;
-
- ipu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- dma_cm: dma_cm@a00 {
- compatible = "ti,omap4-cm";
- reg = <0xa00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xa00 0x100>;
-
- dma_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- emif_cm: emif_cm@b00 {
- compatible = "ti,omap4-cm";
- reg = <0xb00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xb00 0x100>;
-
- emif_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x1c>;
- #clock-cells = <2>;
- };
- };
-
- l4cfg_cm: l4cfg_cm@d00 {
- compatible = "ti,omap4-cm";
- reg = <0xd00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xd00 0x100>;
-
- l4cfg_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x14>;
- #clock-cells = <2>;
- };
- };
-
- l3instr_cm: l3instr_cm@e00 {
- compatible = "ti,omap4-cm";
- reg = <0xe00 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0xe00 0x100>;
-
- l3instr_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0xc>;
- #clock-cells = <2>;
- };
- };
-
- l4per_cm: clock@1000 {
- compatible = "ti,omap4-cm";
- reg = <0x1000 0x200>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1000 0x200>;
-
- l4per_clkctrl: clock@20 {
- compatible = "ti,clkctrl-l4per", "ti,clkctrl";
- reg = <0x20 0x15c>;
- #clock-cells = <2>;
- };
-
- l4sec_clkctrl: clock@1a0 {
- compatible = "ti,clkctrl-l4sec", "ti,clkctrl";
- reg = <0x1a0 0x3c>;
- #clock-cells = <2>;
- };
- };
-
- dss_cm: dss_cm@1400 {
- compatible = "ti,omap4-cm";
- reg = <0x1400 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1400 0x100>;
-
- dss_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- gpu_cm: gpu_cm@1500 {
- compatible = "ti,omap4-cm";
- reg = <0x1500 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1500 0x100>;
-
- gpu_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x4>;
- #clock-cells = <2>;
- };
- };
-
- l3init_cm: l3init_cm@1600 {
- compatible = "ti,omap4-cm";
- reg = <0x1600 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1600 0x100>;
-
- l3init_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0xd4>;
- #clock-cells = <2>;
- };
- };
-};
-
-&prm {
- wkupaon_cm: wkupaon_cm@1900 {
- compatible = "ti,omap4-cm";
- reg = <0x1900 0x100>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1900 0x100>;
-
- wkupaon_clkctrl: clk@20 {
- compatible = "ti,clkctrl";
- reg = <0x20 0x5c>;
- #clock-cells = <2>;
- };
- };
-};
-
-&scm_wkup_pad_conf_clocks {
- fref_xtal_ck: fref_xtal_ck {
- #clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&sys_clkin>;
- ti,bit-shift = <28>;
- reg = <0x14>;
- };
-};
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 607af27..3b86b93 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -51,16 +51,21 @@
};
};
- debug_uart: serial@a84000 {
- compatible = "qcom,msm-geni-uart";
- reg = <0xa84000 0x4000>;
- reg-names = "se_phys";
- clock-names = "se-clk";
- clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
- pinctrl-names = "default";
- pinctrl-0 = <&qup_uart9>;
- qcom,wrapper-core = <0x8a>;
- status = "disabled";
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0x00ac0000 0x6000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-debug-uart";
+ reg = <0xa84000 0x4000>;
+ clock-names = "se";
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9>;
+ };
};
spmi@c440000 {
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 34a4f59..eec51d1 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -9,6 +9,8 @@
/dts-v1/;
#include "sdm845.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
/ {
model = "Samsung S9 (SM-G9600)";
@@ -21,7 +23,7 @@
};
aliases {
- serial0 = &debug_uart;
+ serial0 = &uart9;
};
memory {
@@ -43,6 +45,22 @@
format = "a8r8g8b8";
};
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ key-pwr {
+ label = "Power";
+ linux,code = <KEY_ENTER>;
+ gpios = <&pm8998_pon 0 GPIO_ACTIVE_LOW>;
+ };
+
+ key-vol-down {
+ label = "Volume Down";
+ linux,code = <KEY_DOWN>;
+ gpios = <&pm8998_pon 1 GPIO_ACTIVE_LOW>;
+ };
+ };
+
soc: soc {
serial@a84000 {
status = "okay";
diff --git a/arch/arm/mach-histb/Kconfig b/arch/arm/mach-histb/Kconfig
new file mode 100644
index 0000000..012dbfe
--- /dev/null
+++ b/arch/arm/mach-histb/Kconfig
@@ -0,0 +1,39 @@
+if ARCH_HISTB
+
+choice
+ prompt "Select a HiSTB SoC"
+
+config ARCH_HI3798MV2X
+ bool "Hi3798M V2XX series SoC"
+ select ARM64
+ help
+ Support for Hi3798MV2XX series SoCs.
+
+endchoice
+
+if ARCH_HI3798MV2X
+
+choice
+ prompt "Select a Hi3798M V2XX based board"
+
+config TARGET_HC2910_2AGHD05
+ bool "Skyworth HC2910 with board label 2AGHD05"
+ help
+ Support for Skyworth HC2910 with board label 2AGHD05. This board features:
+ - Hisilicon Hi3798MV200 SoC (4xCortex-A53, Mali MP-450)
+ - 2GiB DRAM
+ - 8GiB eMMC, uSD slot
+ - Wifi and Bluetooth module
+ - 1x USB 2.0, 1x USB 3.0 host port
+ - HDMI
+ - SCI
+ - 3 LED - power, Wifi, Lock(?)
+ - 1x Fast Ethernet Controller, 1x GBe Ethernet Controller
+
+endchoice
+
+endif
+
+source "board/skyworth/hc2910-2aghd05/Kconfig"
+
+endif
diff --git a/arch/arm/mach-histb/Makefile b/arch/arm/mach-histb/Makefile
new file mode 100644
index 0000000..7975c0f
--- /dev/null
+++ b/arch/arm/mach-histb/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += sysmap-histb.o
+obj-y += board_common.o
diff --git a/arch/arm/mach-histb/board_common.c b/arch/arm/mach-histb/board_common.c
new file mode 100644
index 0000000..a26c206
--- /dev/null
+++ b/arch/arm/mach-histb/board_common.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for all histb boards
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+
+int __weak board_init(void)
+{
+ return 0;
+}
+
+int __weak dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int __weak dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+void __weak reset_cpu(void)
+{
+ psci_system_reset();
+}
diff --git a/arch/arm/mach-histb/sysmap-histb.c b/arch/arm/mach-histb/sysmap-histb.c
new file mode 100644
index 0000000..83a2bb9
--- /dev/null
+++ b/arch/arm/mach-histb/sysmap-histb.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Hisilicon HiSTB memory map
+ *
+ * (C) Copyright 2023 Yang Xiwen <forbidden405@outlook.com>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region histb_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DRAM */
+ .phys = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL, /* Peripheral block */
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* Terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = histb_mem_map;
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index a89a9b4..1f51b04 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -65,6 +65,20 @@
mmr_unlock(PADCFG_MMR1_BASE, 1);
}
+#if (IS_ENABLED(CONFIG_CPU_V7R))
+static void setup_qos(void)
+{
+ u32 i;
+
+ for (i = 0; i < am62a_qos_count; i++)
+ writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
+}
+#else
+static void setup_qos(void)
+{
+}
+#endif
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -158,6 +172,8 @@
panic("DRAM init failed: %d\n", ret);
#endif
+ setup_qos();
+
printf("am62a_init: %s done\n", __func__);
}
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
index c58e52d..02a9418 100644
--- a/arch/arm/mach-k3/am62ax/Makefile
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -4,3 +4,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += am62a_qos_data.o
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
new file mode 100644
index 0000000..01b76f7
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62a Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#include <common.h>
+#include <asm/arch/hardware.h>
+#include "common.h"
+
+struct k3_qos_data am62a_qos_data[] = {
+ /* modules_qosConfig0 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
+ .val = ORDERID_8,
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
+ .val = 0x76543210,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
+ .val = 0xfedcba98,
+ },
+};
+
+uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index 0c295e7..c871e92 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -20,9 +20,15 @@
#include <dm/pinctrl.h>
#include <mmc.h>
#include <dm/root.h>
+#include <command.h>
#define CTRLMMR_MCU_RST_CTRL 0x04518170
+#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178)
+#define COLD_BOOT 0
+#define SW_POR_MCU BIT(24)
+#define SW_POR_MAIN BIT(25)
+
static void ctrl_mmr_unlock(void)
{
/* Unlock all PADCFG_MMR1 module registers */
@@ -164,6 +170,7 @@
#if defined(CONFIG_K3_LOAD_SYSFW) || defined(CONFIG_K3_AM64_DDRSS) || defined(CONFIG_ESM_K3)
struct udevice *dev;
int ret;
+ int rst_src;
#endif
#if defined(CONFIG_CPU_V7R)
@@ -206,6 +213,32 @@
k3_mmc_restart_clock);
#endif
+#if defined(CONFIG_CPU_V7R)
+ /*
+ * Errata ID i2331 CPSW: A device lockup can occur during the second
+ * read of any CPSW subsystem register after any MAIN domain power on
+ * reset (POR). A MAIN domain POR occurs using the hardware MCU_PORz
+ * signal, or via software using CTRLMMR_RST_CTRL.SW_MAIN_POR or
+ * CTRLMMR_MCU_RST_CTRL.SW_MAIN_POR. After these resets, the processor
+ * and internal bus structures may get into a state which is only
+ * recoverable with full device reset using MCU_PORz.
+ * Workaround(s): To avoid the lockup, a warm reset should be issued
+ * after a MAIN domain POR and before any access to the CPSW registers.
+ * The warm reset realigns internal clocks and prevents the lockup from
+ * happening.
+ */
+ ret = uclass_first_device_err(UCLASS_SYSRESET, &dev);
+ if (ret)
+ printf("\n%s:uclass device error [%d]\n",__func__,ret);
+
+ rst_src = readl(CTRLMMR_MCU_RST_SRC);
+ if (rst_src == COLD_BOOT || rst_src & (SW_POR_MCU | SW_POR_MAIN)) {
+ printf("Resetting on cold boot to workaround ErrataID:i2331\n");
+ printf("Please resend tiboot3.bin in case of UART/DFU boot\n");
+ do_reset(NULL, 0, 0, NULL);
+ }
+#endif
+
/* Output System Firmware version info */
k3_sysfw_print_ver();
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c
index 7baab7d..3c85cae 100644
--- a/arch/arm/mach-k3/common.c
+++ b/arch/arm/mach-k3/common.c
@@ -580,7 +580,10 @@
fwl_ops->get_fwl_region(ti_sci, ®ion);
- if (region.control != 0) {
+ /* Don't disable the background regions */
+ if (region.control != 0 &&
+ ((region.control & K3_BACKGROUND_FIREWALL_BIT) ==
+ 0)) {
pr_debug("Attempting to disable firewall %5d (%25s)\n",
region.fwl_id, fwl_data[i].name);
region.control = 0;
@@ -641,8 +644,8 @@
printf("Failed to probe am65_cpsw_nuss driver\n");
}
- /* Default FIT boot on non-GP devices */
- if (get_device_type() != K3_DEVICE_TYPE_GP)
+ /* Default FIT boot on HS-SE devices */
+ if (get_device_type() == K3_DEVICE_TYPE_HS_SE)
env_set("boot_fit", "1");
return 0;
diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h
index 130f502..e7e59f5 100644
--- a/arch/arm/mach-k3/common.h
+++ b/arch/arm/mach-k3/common.h
@@ -9,6 +9,10 @@
#include <asm/armv7_mpu.h>
#include <asm/hardware.h>
+#define J721E 0xbb64
+#define J7200 0xbb6d
+#define K3_BACKGROUND_FIREWALL_BIT BIT(8)
+
struct fwl_data {
const char *name;
u16 fwl_id;
diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h b/arch/arm/mach-k3/include/mach/am62a_qos.h
new file mode 100644
index 0000000..c74d69a
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62a_qos.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0 (0 << 0)
+#define QOS_1 (1 << 0)
+#define QOS_2 (2 << 0)
+#define QOS_3 (3 << 0)
+#define QOS_4 (4 << 0)
+#define QOS_5 (5 << 0)
+#define QOS_6 (6 << 0)
+#define QOS_7 (7 << 0)
+
+#define ORDERID_0 (0 << 4)
+#define ORDERID_1 (1 << 4)
+#define ORDERID_2 (2 << 4)
+#define ORDERID_3 (3 << 4)
+#define ORDERID_4 (4 << 4)
+#define ORDERID_5 (5 << 4)
+#define ORDERID_6 (6 << 4)
+#define ORDERID_7 (7 << 4)
+#define ORDERID_8 (8 << 4)
+#define ORDERID_9 (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10 (10 << 8)
+#define ASEL_11 (11 << 8)
+#define ASEL_12 (12 << 8)
+#define ASEL_13 (13 << 8)
+#define ASEL_14 (14 << 8)
+#define ASEL_15 (15 << 8)
+
+#define EPRIORITY_0 (0 << 12)
+#define EPRIORITY_1 (1 << 12)
+#define EPRIORITY_2 (2 << 12)
+#define EPRIORITY_3 (3 << 12)
+#define EPRIORITY_4 (4 << 12)
+#define EPRIORITY_5 (5 << 12)
+#define EPRIORITY_6 (6 << 12)
+#define EPRIORITY_7 (7 << 12)
+
+#define VIRTID_0 (0 << 16)
+#define VIRTID_1 (1 << 16)
+#define VIRTID_2 (2 << 16)
+#define VIRTID_3 (3 << 16)
+#define VIRTID_4 (4 << 16)
+#define VIRTID_5 (5 << 16)
+#define VIRTID_6 (6 << 16)
+#define VIRTID_7 (7 << 16)
+#define VIRTID_8 (8 << 16)
+#define VIRTID_9 (9 << 16)
+#define VIRTID_10 (10 << 16)
+#define VIRTID_11 (11 << 16)
+#define VIRTID_12 (12 << 16)
+#define VIRTID_13 (13 << 16)
+#define VIRTID_14 (14 << 16)
+#define VIRTID_15 (15 << 16)
+
+#define ATYPE_0 (0 << 28)
+#define ATYPE_1 (1 << 28)
+#define ATYPE_2 (2 << 28)
+#define ATYPE_3 (3 << 28)
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
+#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000
+#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400
+#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800
+#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
+#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
+#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 9faf1d6..65742c4 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -30,6 +30,7 @@
#ifdef CONFIG_SOC_K3_AM62A7
#include "am62a_hardware.h"
+#include "am62a_qos.h"
#endif
/* Assuming these addresses and definitions stay common across K3 devices */
@@ -96,4 +97,12 @@
u32 num_components;
};
+struct k3_qos_data {
+ u32 reg;
+ u32 val;
+};
+
+extern struct k3_qos_data am62a_qos_data[];
+extern u32 am62a_qos_count;
+
#endif /* _ASM_ARCH_HARDWARE_H_ */
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index 9bba5f7..0c5d41a 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -25,6 +25,7 @@
#ifdef CONFIG_K3_LOAD_SYSFW
struct fwl_data cbass_hc_cfg0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
{ "PCIE0_CFG", 2560, 8 },
{ "PCIE1_CFG", 2561, 8 },
{ "USB3SS0_CORE", 2568, 4 },
@@ -33,11 +34,16 @@
{ "UFS_HCI0_CFG", 2580, 4 },
{ "SERDES0", 2584, 1 },
{ "SERDES1", 2585, 1 },
+#elif defined(CONFIG_TARGET_J7200_R5_EVM)
+ { "PCIE1_CFG", 2561, 7 },
+#endif
}, cbass_hc0_fwls[] = {
+#if defined(CONFIG_TARGET_J721E_R5_EVM)
{ "PCIE0_HP", 2528, 24 },
{ "PCIE0_LP", 2529, 24 },
{ "PCIE1_HP", 2530, 24 },
{ "PCIE1_LP", 2531, 24 },
+#endif
}, cbass_rc_cfg0_fwls[] = {
{ "EMMCSD4SS0_CFG", 2380, 4 },
}, cbass_rc0_fwls[] = {
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index 0787d19..5394529 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -17,9 +17,6 @@
config TARGET_CM_T54
bool "CompuLab CM-T54"
-config TARGET_OMAP5_UEVM
- bool "TI OMAP5 uEVM board"
-
config TARGET_DRA7XX_EVM
bool "TI DRA7XX"
select BOARD_LATE_INIT
@@ -162,7 +159,6 @@
endmenu
endif
-source "board/ti/omap5_uevm/Kconfig"
source "board/ti/dra7xx/Kconfig"
source "board/ti/am57xx/Kconfig"
diff --git a/arch/powerpc/cpu/mpc83xx/bats/Kconfig b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
index 218920c..1cdb390 100644
--- a/arch/powerpc/cpu/mpc83xx/bats/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/bats/Kconfig
@@ -65,18 +65,12 @@
endchoice
-config BAT0_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT0_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT0_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT0_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT0_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -120,22 +114,10 @@
config BAT0_WIMG_ICACHE
hex
- default 0x0 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x8 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x10 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x18 if !BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x20 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x28 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x30 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x38 if !BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x40 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x48 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x50 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x58 if BAT0_ICACHE_WRITETHROUGH && !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x60 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x68 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
- default 0x70 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && !BAT0_ICACHE_GUARDED
- default 0x78 if BAT0_ICACHE_WRITETHROUGH && BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE && BAT0_ICACHE_GUARDED
+ default 0x0 if !BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT0_ICACHE_INHIBITED && !BAT0_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT0_ICACHE_INHIBITED && BAT0_ICACHE_MEMORYCOHERENCE
config BAT0_WIMG_DCACHE
hex
@@ -228,18 +210,12 @@
endchoice
-config BAT1_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT1_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT1_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT1_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT1_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -283,22 +259,10 @@
config BAT1_WIMG_ICACHE
hex
- default 0x0 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x8 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x10 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x18 if !BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x20 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x28 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x30 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x38 if !BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x40 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x48 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x50 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x58 if BAT1_ICACHE_WRITETHROUGH && !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x60 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x68 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
- default 0x70 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && !BAT1_ICACHE_GUARDED
- default 0x78 if BAT1_ICACHE_WRITETHROUGH && BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE && BAT1_ICACHE_GUARDED
+ default 0x0 if !BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT1_ICACHE_INHIBITED && !BAT1_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT1_ICACHE_INHIBITED && BAT1_ICACHE_MEMORYCOHERENCE
config BAT1_WIMG_DCACHE
hex
@@ -391,18 +355,12 @@
endchoice
-config BAT2_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT2_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT2_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT2_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT2_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -446,22 +404,10 @@
config BAT2_WIMG_ICACHE
hex
- default 0x0 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x8 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x10 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x18 if !BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x20 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x28 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x30 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x38 if !BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x40 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x48 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x50 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x58 if BAT2_ICACHE_WRITETHROUGH && !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x60 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x68 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
- default 0x70 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && !BAT2_ICACHE_GUARDED
- default 0x78 if BAT2_ICACHE_WRITETHROUGH && BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE && BAT2_ICACHE_GUARDED
+ default 0x0 if !BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT2_ICACHE_INHIBITED && !BAT2_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT2_ICACHE_INHIBITED && BAT2_ICACHE_MEMORYCOHERENCE
config BAT2_WIMG_DCACHE
hex
@@ -554,18 +500,12 @@
endchoice
-config BAT3_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT3_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT3_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT3_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT3_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -609,22 +549,10 @@
config BAT3_WIMG_ICACHE
hex
- default 0x0 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x8 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x10 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x18 if !BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x20 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x28 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x30 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x38 if !BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x40 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x48 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x50 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x58 if BAT3_ICACHE_WRITETHROUGH && !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x60 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x68 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
- default 0x70 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && !BAT3_ICACHE_GUARDED
- default 0x78 if BAT3_ICACHE_WRITETHROUGH && BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE && BAT3_ICACHE_GUARDED
+ default 0x0 if !BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT3_ICACHE_INHIBITED && !BAT3_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT3_ICACHE_INHIBITED && BAT3_ICACHE_MEMORYCOHERENCE
config BAT3_WIMG_DCACHE
hex
@@ -719,18 +647,12 @@
endchoice
-config BAT4_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT4_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT4_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT4_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT4_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -774,22 +696,10 @@
config BAT4_WIMG_ICACHE
hex
- default 0x0 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x8 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x10 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x18 if !BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x20 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x28 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x30 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x38 if !BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x40 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x48 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x50 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x58 if BAT4_ICACHE_WRITETHROUGH && !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x60 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x68 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
- default 0x70 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && !BAT4_ICACHE_GUARDED
- default 0x78 if BAT4_ICACHE_WRITETHROUGH && BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE && BAT4_ICACHE_GUARDED
+ default 0x0 if !BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT4_ICACHE_INHIBITED && !BAT4_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT4_ICACHE_INHIBITED && BAT4_ICACHE_MEMORYCOHERENCE
config BAT4_WIMG_DCACHE
hex
@@ -882,18 +792,12 @@
endchoice
-config BAT5_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT5_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT5_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT5_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT5_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -937,22 +841,10 @@
config BAT5_WIMG_ICACHE
hex
- default 0x0 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x8 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x10 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x18 if !BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x20 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x28 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x30 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x38 if !BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x40 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x48 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x50 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x58 if BAT5_ICACHE_WRITETHROUGH && !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x60 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x68 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
- default 0x70 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && !BAT5_ICACHE_GUARDED
- default 0x78 if BAT5_ICACHE_WRITETHROUGH && BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE && BAT5_ICACHE_GUARDED
+ default 0x0 if !BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT5_ICACHE_INHIBITED && !BAT5_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT5_ICACHE_INHIBITED && BAT5_ICACHE_MEMORYCOHERENCE
config BAT5_WIMG_DCACHE
hex
@@ -1045,18 +937,12 @@
endchoice
-config BAT6_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT6_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT6_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT6_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT6_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -1100,22 +986,10 @@
config BAT6_WIMG_ICACHE
hex
- default 0x0 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x8 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x10 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x18 if !BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x20 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x28 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x30 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x38 if !BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x40 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x48 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x50 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x58 if BAT6_ICACHE_WRITETHROUGH && !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x60 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x68 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
- default 0x70 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && !BAT6_ICACHE_GUARDED
- default 0x78 if BAT6_ICACHE_WRITETHROUGH && BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE && BAT6_ICACHE_GUARDED
+ default 0x0 if !BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT6_ICACHE_INHIBITED && !BAT6_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT6_ICACHE_INHIBITED && BAT6_ICACHE_MEMORYCOHERENCE
config BAT6_WIMG_DCACHE
hex
@@ -1208,18 +1082,12 @@
endchoice
-config BAT7_ICACHE_WRITETHROUGH
- bool "I-cache Write-through"
-
config BAT7_ICACHE_INHIBITED
bool "I-cache Inhibited"
config BAT7_ICACHE_MEMORYCOHERENCE
bool "I-cache Memory coherence"
-config BAT7_ICACHE_GUARDED
- bool "I-cache Guarded"
-
config BAT7_DCACHE_WRITETHROUGH
bool "D-cache Write-through"
@@ -1263,22 +1131,10 @@
config BAT7_WIMG_ICACHE
hex
- default 0x0 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x8 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x10 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x18 if !BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x20 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x28 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x30 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x38 if !BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x40 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x48 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x50 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x58 if BAT7_ICACHE_WRITETHROUGH && !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x60 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x68 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
- default 0x70 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && !BAT7_ICACHE_GUARDED
- default 0x78 if BAT7_ICACHE_WRITETHROUGH && BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE && BAT7_ICACHE_GUARDED
+ default 0x0 if !BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE
+ default 0x10 if !BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE
+ default 0x20 if BAT7_ICACHE_INHIBITED && !BAT7_ICACHE_MEMORYCOHERENCE
+ default 0x30 if BAT7_ICACHE_INHIBITED && BAT7_ICACHE_MEMORYCOHERENCE
config BAT7_WIMG_DCACHE
hex
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index bcdea0b..453e53d 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -1816,6 +1816,10 @@
lba_shift = <9>;
lba = <2048>;
};
+
+ extcon {
+ compatible = "sandbox,extcon";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/board/broadcom/bcmns/Kconfig b/board/broadcom/bcmns/Kconfig
new file mode 100644
index 0000000..82f4709
--- /dev/null
+++ b/board/broadcom/bcmns/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BCMNS
+
+config SYS_BOARD
+ default "bcmns"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_CONFIG_NAME
+ default "bcmns"
+
+endif
diff --git a/board/broadcom/bcmns/MAINTAINERS b/board/broadcom/bcmns/MAINTAINERS
new file mode 100644
index 0000000..fd37c33
--- /dev/null
+++ b/board/broadcom/bcmns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCMNS BOARD
+M: Linus Walleij <linus.walleij@linaro.org>
+S: Maintained
+F: board/broadcom/bcmnsp/
+F: configs/bcmnsp_defconfig
+F: include/configs/bcmnsp.h
diff --git a/board/broadcom/bcmns/Makefile b/board/broadcom/bcmns/Makefile
new file mode 100644
index 0000000..8a6a854
--- /dev/null
+++ b/board/broadcom/bcmns/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y := ns.o
diff --git a/board/broadcom/bcmns/ns.c b/board/broadcom/bcmns/ns.c
new file mode 100644
index 0000000..1249e45
--- /dev/null
+++ b/board/broadcom/bcmns/ns.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Broadcom Northstar generic board set-up code
+ * Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int board_late_init(void)
+{
+ /* LEDs etc can be initialized here */
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+int print_cpuinfo(void)
+{
+ printf("BCMNS Northstar SoC\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+ printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt);
+ return 0;
+}
+
diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile
index 0abefda..fe585ad 100644
--- a/board/qualcomm/dragonboard845c/Makefile
+++ b/board/qualcomm/dragonboard845c/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
#
# This empty file prevents make error.
-# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far.
+# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for dragonboard845c so far.
#
obj-y += dragonboard845c.o
diff --git a/board/samsung/starqltechn/Makefile b/board/samsung/starqltechn/Makefile
index c38c0b4..e017c82 100644
--- a/board/samsung/starqltechn/Makefile
+++ b/board/samsung/starqltechn/Makefile
@@ -3,7 +3,7 @@
# (C) Copyright 2021 Dzmitry Sankouski <dsankouski@gmail.com>
#
# This empty file prevents make error.
-# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for starqltechn so far.
+# Board logic defined in arch/arm/mach-snapdragon/init_sdm845.c, no custom logic for starqltechn so far.
#
obj-y += starqltechn.o
diff --git a/board/skyworth/hc2910-2aghd05/Kconfig b/board/skyworth/hc2910-2aghd05/Kconfig
new file mode 100644
index 0000000..f85f1f2
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_HC2910_2AGHD05
+
+config SYS_BOARD
+ default "hc2910-2aghd05"
+
+config SYS_VENDOR
+ default "skyworth"
+
+config SYS_SOC
+ default "hi3798mv200"
+
+config SYS_CONFIG_NAME
+ default "hc2910-2aghd05"
+
+endif
diff --git a/board/skyworth/hc2910-2aghd05/MAINTAINERS b/board/skyworth/hc2910-2aghd05/MAINTAINERS
new file mode 100644
index 0000000..2c1e750
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/MAINTAINERS
@@ -0,0 +1,6 @@
+HC2910 2AGHD05 BOARD
+M: Yang Xiwen <firbidden405@outlook.com>
+S: Maintained
+F: board/skyworth/hc2910-2aghd05
+F: include/configs/hc2910-2aghd05.h
+F: configs/hc2910_2aghd05_defconfig
diff --git a/board/skyworth/hc2910-2aghd05/Makefile b/board/skyworth/hc2910-2aghd05/Makefile
new file mode 100644
index 0000000..193fd15
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/Makefile
@@ -0,0 +1 @@
+obj-y := hc2910-2aghd05.o
diff --git a/board/skyworth/hc2910-2aghd05/README b/board/skyworth/hc2910-2aghd05/README
new file mode 100644
index 0000000..a838956
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/README
@@ -0,0 +1,25 @@
+================================================================================
+ Board Information
+================================================================================
+
+The board features the Hi3798M V200 with an integrated quad-core 64-bit ARM
+Cortex A53 processor.
+SOC Hisilicon Hi3798CV200
+CPU Quad-core ARM Cortex-A53 64 bit
+DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB
+USB 1x USB 2.0 ports 1x USB 3.0 ports
+CONSOLE USB-micro port for console support
+ETHERNET 1 GBe Ethernet, 1 MBe Ethernet
+WIFI 802.11n with Bluebooth
+CONNECTORS One connector for Smart Card One connector for TSI
+
+
+================================================================================
+ BUILD INSTRUCTIONS
+================================================================================
+
+The U-Boot relies on a modified l-loader and TF-A for Hi3798MV200.
+The source for l-loader can be obtained at: [l-loader](https://github.com/185264646/l-loader)
+The mainline port for TF-A is still under development. For now, you can use the TF-A for poplar directly.
+
+For more information, please refer to <board/hisilicon/poplar/README>.
diff --git a/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
new file mode 100644
index 0000000..abad5ef
--- /dev/null
+++ b/board/skyworth/hc2910-2aghd05/hc2910-2aghd05.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for Skyworth HC2910 2AGHD05
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <asm/system.h>
+#include <linux/io.h>
+
+#define HI3798MV200_PERI_CTRL_BASE 0xf8a20000
+#define SDIO0_LDO_OFFSET 0x11c
+
+static int sdio0_set_ldo(void)
+{
+ // SDIO LDO bypassed, 3.3V
+ writel(HI3798MV200_PERI_CTRL_BASE + SDIO0_LDO_OFFSET, 0x60);
+ return 0;
+}
+
+int board_init(void)
+{
+ sdio0_set_ldo();
+ return 0;
+}
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c
index 09d2688..8eaca9d 100644
--- a/board/ti/j721s2/evm.c
+++ b/board/ti/j721s2/evm.c
@@ -153,6 +153,135 @@
snprintf(serial_string, sizeof(serial_string), "%016lx", board_serial);
env_set("serial#", serial_string);
}
+
+/*
+ * Declaration of daughtercards to probe. Note that when adding more
+ * cards they should be grouped by the 'i2c_addr' field to allow for a
+ * more efficient probing process.
+ */
+static const struct {
+ u8 i2c_addr; /* I2C address of card EEPROM */
+ char *card_name; /* EEPROM-programmed card name */
+ char *dtbo_name; /* Device tree overlay to apply */
+ u8 eth_offset; /* ethXaddr MAC address index offset */
+} ext_cards[] = {
+ {
+ 0x52,
+ "J7X-GESI-EXP",
+ "k3-j721s2-gesi-exp-board.dtbo",
+ 1, /* Start populating from eth1addr */
+ },
+};
+
+#define DAUGHTER_CARD_NO_OF_MAC_ADDR 5
+static bool daughter_card_detect_flags[ARRAY_SIZE(ext_cards)];
+
+static int probe_daughtercards(void)
+{
+ char mac_addr[DAUGHTER_CARD_NO_OF_MAC_ADDR][TI_EEPROM_HDR_ETH_ALEN];
+ bool eeprom_read_success;
+ struct ti_am6_eeprom ep;
+ u8 previous_i2c_addr;
+ u8 mac_addr_cnt;
+ int i;
+ int ret;
+
+ /* Mark previous I2C address variable as not populated */
+ previous_i2c_addr = 0xff;
+
+ /* No EEPROM data was read yet */
+ eeprom_read_success = false;
+
+ /* Iterate through list of daughtercards */
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ /* Obtain card-specific I2C address */
+ u8 i2c_addr = ext_cards[i].i2c_addr;
+
+ /* Read card EEPROM if not already read previously */
+ if (i2c_addr != previous_i2c_addr) {
+ /* Store I2C address so we can avoid reading twice */
+ previous_i2c_addr = i2c_addr;
+
+ /* Get and parse the daughter card EEPROM record */
+ ret = ti_i2c_eeprom_am6_get(CONFIG_EEPROM_BUS_ADDRESS,
+ i2c_addr,
+ &ep,
+ (char **)mac_addr,
+ DAUGHTER_CARD_NO_OF_MAC_ADDR,
+ &mac_addr_cnt);
+ if (ret) {
+ debug("%s: No daughtercard EEPROM at 0x%02x found %d\n",
+ __func__, i2c_addr, ret);
+ eeprom_read_success = false;
+ /* Skip to the next daughtercard to probe */
+ continue;
+ }
+
+ /* EEPROM read successful, okay to further process. */
+ eeprom_read_success = true;
+ }
+
+ /* Only continue processing if EEPROM data was read */
+ if (!eeprom_read_success)
+ continue;
+
+ /* Only process the parsed data if we found a match */
+ if (strncmp(ep.name, ext_cards[i].card_name, sizeof(ep.name)))
+ continue;
+
+ printf("Detected: %s rev %s\n", ep.name, ep.version);
+ daughter_card_detect_flags[i] = true;
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ int j;
+ /*
+ * Populate any MAC addresses from daughtercard into the U-Boot
+ * environment, starting with a card-specific offset so we can
+ * have multiple ext_cards contribute to the MAC pool in a well-
+ * defined manner.
+ */
+ for (j = 0; j < mac_addr_cnt; j++) {
+ if (!is_valid_ethaddr((u8 *)mac_addr[j]))
+ continue;
+
+ eth_env_set_enetaddr_by_index("eth", ext_cards[i].eth_offset + j,
+ (uchar *)mac_addr[j]);
+ }
+ }
+ }
+
+ if (!IS_ENABLED(CONFIG_SPL_BUILD)) {
+ char name_overlays[1024] = { 0 };
+
+ for (i = 0; i < ARRAY_SIZE(ext_cards); i++) {
+ if (!daughter_card_detect_flags[i])
+ continue;
+
+ /* Skip if no overlays are to be added */
+ if (!strlen(ext_cards[i].dtbo_name))
+ continue;
+
+ /*
+ * Make sure we are not running out of buffer space by checking
+ * if we can fit the new overlay, a trailing space to be used
+ * as a separator, plus the terminating zero.
+ */
+ if (strlen(name_overlays) + strlen(ext_cards[i].dtbo_name) + 2 >
+ sizeof(name_overlays))
+ return -ENOMEM;
+
+ /* Append to our list of overlays */
+ strcat(name_overlays, ext_cards[i].dtbo_name);
+ strcat(name_overlays, " ");
+ }
+
+ /* Apply device tree overlay(s) to the U-Boot environment, if any */
+ if (strlen(name_overlays))
+ return env_set("name_overlays", name_overlays);
+ }
+
+ return 0;
+}
#endif
/*
@@ -182,6 +311,7 @@
if (IS_ENABLED(CONFIG_TI_I2C_BOARD_DETECT)) {
setup_board_eeprom_env();
setup_serial();
+ probe_daughtercards();
}
return 0;
diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig
deleted file mode 100644
index aa13844..0000000
--- a/board/ti/omap5_uevm/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_OMAP5_UEVM
-
-config SYS_BOARD
- default "omap5_uevm"
-
-config SYS_VENDOR
- default "ti"
-
-config SYS_CONFIG_NAME
- default "omap5_uevm"
-
-endif
diff --git a/board/ti/omap5_uevm/MAINTAINERS b/board/ti/omap5_uevm/MAINTAINERS
deleted file mode 100644
index ce54482..0000000
--- a/board/ti/omap5_uevm/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-OMAP5_UEVM BOARD
-M: Tom Rini <trini@konsulko.com>
-S: Maintained
-F: board/ti/omap5_uevm/
-F: include/configs/omap5_uevm.h
-F: configs/omap5_uevm_defconfig
diff --git a/board/ti/omap5_uevm/Makefile b/board/ti/omap5_uevm/Makefile
deleted file mode 100644
index 17ee516..0000000
--- a/board/ti/omap5_uevm/Makefile
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0+
-#
-# (C) Copyright 2000, 2001, 2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-
-obj-y := evm.o
diff --git a/board/ti/omap5_uevm/README b/board/ti/omap5_uevm/README
deleted file mode 100644
index 970e2ec..0000000
--- a/board/ti/omap5_uevm/README
+++ /dev/null
@@ -1,25 +0,0 @@
-Summary
-=======
-
-This document covers various features of the 'omap5_uevm' build and some
-related uses.
-
-eMMC boot partition use
-=======================
-
-It is possible, depending on SYSBOOT configuration to boot from the eMMC
-boot partitions using (name depending on documentation referenced)
-Alternative Boot operation mode or Boot Sequence Option 1/2. In this
-example we load MLO and u-boot.img from the build into DDR and then use
-'mmc bootbus' to set the required rate (see TRM) and 'mmc partconfig' to
-set boot0 as the boot device.
-U-Boot # setenv autoload no
-U-Boot # usb start
-U-Boot # dhcp
-U-Boot # mmc dev 1 1
-U-Boot # tftp ${loadaddr} omap5uevm/MLO
-U-Boot # mmc write ${loadaddr} 0 100
-U-Boot # tftp ${loadaddr} omap5uevm/u-boot.img
-U-Boot # mmc write ${loadaddr} 300 400
-U-Boot # mmc bootbus 1 2 0 2
-U-Boot # mmc partconf 1 1 1 0
diff --git a/board/ti/omap5_uevm/evm.c b/board/ti/omap5_uevm/evm.c
deleted file mode 100644
index 09cbd6b..0000000
--- a/board/ti/omap5_uevm/evm.c
+++ /dev/null
@@ -1,226 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- * Aneesh V <aneesh@ti.com>
- * Steve Sakoman <steve@sakoman.com>
- */
-#include <common.h>
-#include <init.h>
-#include <net.h>
-#include <palmas.h>
-#include <asm/arch/omap.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/mmc_host_def.h>
-#include <serial.h>
-#include <tca642x.h>
-#include <usb.h>
-#include <asm/global_data.h>
-#include <linux/delay.h>
-#include <linux/usb/gadget.h>
-#include <dwc3-uboot.h>
-#include <dwc3-omap-uboot.h>
-#include <ti-usb-phy-uboot.h>
-
-#include "mux_data.h"
-
-#if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_XHCI_OMAP)
-#include <sata.h>
-#include <usb.h>
-#include <asm/gpio.h>
-#include <asm/mach-types.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/ehci.h>
-#include <asm/ehci-omap.h>
-#include <asm/arch/sata.h>
-
-#define DIE_ID_REG_BASE (OMAP54XX_L4_CORE_BASE + 0x2000)
-#define DIE_ID_REG_OFFSET 0x200
-
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const struct omap_sysinfo sysinfo = {
- "Board: OMAP5432 uEVM\n"
-};
-
-/**
- * @brief tca642x_init - uEVM default values for the GPIO expander
- * input reg, output reg, polarity reg, configuration reg
- */
-struct tca642x_bank_info tca642x_init[] = {
- { .input_reg = 0x00,
- .output_reg = 0x04,
- .polarity_reg = 0x00,
- .configuration_reg = 0x80 },
- { .input_reg = 0x00,
- .output_reg = 0x00,
- .polarity_reg = 0x00,
- .configuration_reg = 0xff },
- { .input_reg = 0x00,
- .output_reg = 0x00,
- .polarity_reg = 0x00,
- .configuration_reg = 0x40 },
-};
-
-#ifdef CONFIG_USB_DWC3
-static struct dwc3_device usb_otg_ss = {
- .maximum_speed = USB_SPEED_SUPER,
- .base = OMAP5XX_USB_OTG_SS_BASE,
- .tx_fifo_resize = false,
- .index = 0,
-};
-
-static struct dwc3_omap_device usb_otg_ss_glue = {
- .base = (void *)OMAP5XX_USB_OTG_SS_GLUE_BASE,
- .utmi_mode = DWC3_OMAP_UTMI_MODE_SW,
- .index = 0,
-};
-
-static struct ti_usb_phy_device usb_phy_device = {
- .pll_ctrl_base = (void *)OMAP5XX_USB3_PHY_PLL_CTRL,
- .usb2_phy_power = (void *)OMAP5XX_USB2_PHY_POWER,
- .usb3_phy_power = (void *)OMAP5XX_USB3_PHY_POWER,
- .index = 0,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
- if (index) {
- printf("Invalid Controller Index\n");
- return -EINVAL;
- }
-
- if (init == USB_INIT_DEVICE) {
- usb_otg_ss.dr_mode = USB_DR_MODE_PERIPHERAL;
- usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_VBUS_VALID;
- } else {
- usb_otg_ss.dr_mode = USB_DR_MODE_HOST;
- usb_otg_ss_glue.vbus_id_status = OMAP_DWC3_ID_GROUND;
- }
-
- enable_usb_clocks(index);
- ti_usb_phy_uboot_init(&usb_phy_device);
- dwc3_omap_uboot_init(&usb_otg_ss_glue);
- dwc3_uboot_init(&usb_otg_ss);
-
- return 0;
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
- if (index) {
- printf("Invalid Controller Index\n");
- return -EINVAL;
- }
-
- ti_usb_phy_uboot_exit(index);
- dwc3_uboot_exit(index);
- dwc3_omap_uboot_exit(index);
- disable_usb_clocks(index);
-
- return 0;
-}
-
-int usb_gadget_handle_interrupts(int index)
-{
- u32 status;
-
- status = dwc3_omap_uboot_interrupt_status(index);
- if (status)
- dwc3_uboot_handle_interrupt(index);
-
- return 0;
-}
-#endif
-
-/**
- * @brief board_init
- *
- * Return: 0
- */
-int board_init(void)
-{
- gpmc_init();
- gd->bd->bi_arch_number = MACH_TYPE_OMAP5_SEVM;
- gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
-
- tca642x_set_inital_state(CFG_SYS_I2C_TCA642X_ADDR, tca642x_init);
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_OS_BOOT)
-int spl_start_uboot(void)
-{
- /* break into full u-boot on 'c' */
- if (serial_tstc() && serial_getc() == 'c')
- return 1;
-
- return 0;
-}
-#endif /* CONFIG_SPL_OS_BOOT */
-
-int board_eth_init(struct bd_info *bis)
-{
- return 0;
-}
-
-/**
- * @brief misc_init_r - Configure EVM board specific configurations
- * such as power configurations, ethernet initialization as phase2 of
- * boot sequence
- *
- * Return: 0
- */
-int misc_init_r(void)
-{
-#ifdef CONFIG_PALMAS_POWER
- palmas_init_settings();
-#endif
-
- omap_die_id_usbethaddr();
-
- return 0;
-}
-
-void set_muxconf_regs(void)
-{
- do_set_mux((*ctrl)->control_padconf_core_base,
- core_padconf_array_essential,
- sizeof(core_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-
- do_set_mux((*ctrl)->control_padconf_wkup_base,
- wkup_padconf_array_essential,
- sizeof(wkup_padconf_array_essential) /
- sizeof(struct pad_conf_entry));
-}
-
-#if defined(CONFIG_MMC)
-int board_mmc_init(struct bd_info *bis)
-{
- omap_mmc_init(0, 0, 0, -1, -1);
- omap_mmc_init(1, 0, 0, -1, -1);
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_OMAP
-/**
- * @brief board_usb_init - Configure EVM board specific configurations
- * for the LDO's and clocks for the USB blocks.
- *
- * Return: 0
- */
-int board_usb_init(int index, enum usb_init_type init)
-{
- int ret;
-#ifdef CONFIG_PALMAS_USB_SS_PWR
- ret = palmas_enable_ss_ldo();
-#endif
-
- return 0;
-}
-#endif
diff --git a/board/ti/omap5_uevm/mux_data.h b/board/ti/omap5_uevm/mux_data.h
deleted file mode 100644
index 3c4ba47..0000000
--- a/board/ti/omap5_uevm/mux_data.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2010
- * Texas Instruments Incorporated, <www.ti.com>
- *
- * Sricharan R <r.sricharan@ti.com>
- */
-#ifndef _EVM5430_MUX_DATA_H
-#define _EVM5430_MUX_DATA_H
-
-#include <asm/arch/mux_omap5.h>
-
-const struct pad_conf_entry core_padconf_array_essential[] = {
-
- {EMMC_CLK, (PTU | IEN | M0)}, /* EMMC_CLK */
- {EMMC_CMD, (PTU | IEN | M0)}, /* EMMC_CMD */
- {EMMC_DATA0, (PTU | IEN | M0)}, /* EMMC_DATA0 */
- {EMMC_DATA1, (PTU | IEN | M0)}, /* EMMC_DATA1 */
- {EMMC_DATA2, (PTU | IEN | M0)}, /* EMMC_DATA2 */
- {EMMC_DATA3, (PTU | IEN | M0)}, /* EMMC_DATA3 */
- {EMMC_DATA4, (PTU | IEN | M0)}, /* EMMC_DATA4 */
- {EMMC_DATA5, (PTU | IEN | M0)}, /* EMMC_DATA5 */
- {EMMC_DATA6, (PTU | IEN | M0)}, /* EMMC_DATA6 */
- {EMMC_DATA7, (PTU | IEN | M0)}, /* EMMC_DATA7 */
- {SDCARD_CLK, (PTU | IEN | M0)}, /* SDCARD_CLK */
- {SDCARD_CMD, (PTU | IEN | M0)}, /* SDCARD_CMD */
- {SDCARD_DATA0, (PTU | IEN | M0)}, /* SDCARD_DATA0*/
- {SDCARD_DATA1, (PTU | IEN | M0)}, /* SDCARD_DATA1*/
- {SDCARD_DATA2, (PTU | IEN | M0)}, /* SDCARD_DATA2*/
- {SDCARD_DATA3, (PTU | IEN | M0)}, /* SDCARD_DATA3*/
- {UART3_RX_IRRX, (PTU | IEN | M0)}, /* UART3_RX_IRRX */
- {UART3_TX_IRTX, (M0)}, /* UART3_TX_IRTX */
- {USBB1_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB1_HSIC_STROBE */
- {USBB1_HSIC_DATA, (PTU | IEN | M0)}, /* USBB1_HSIC_DATA */
- {USBB2_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB2_HSIC_STROBE */
- {USBB2_HSIC_DATA, (PTU | IEN | M0)}, /* USBB2_HSIC_DATA */
- {USBB3_HSIC_STROBE, (PTU | IEN | M0)}, /* USBB3_HSIC_STROBE*/
- {USBB3_HSIC_DATA, (PTU | IEN | M0)}, /* USBB3_HSIC_DATA */
- {USBD0_HS_DP, (IEN | M0)}, /* USBD0_HS_DP */
- {USBD0_HS_DM, (IEN | M0)}, /* USBD0_HS_DM */
- {USBD0_SS_RX, (IEN | M0)}, /* USBD0_SS_RX */
- {I2C5_SCL, (IEN | M0)}, /* I2C5_SCL */
- {I2C5_SDA, (IEN | M0)}, /* I2C5_SDA */
- {HSI2_ACWAKE, (PTU | M6)}, /* HSI2_ACWAKE */
- {HSI2_CAFLAG, (PTU | M6)}, /* HSI2_CAFLAG */
-};
-
-const struct pad_conf_entry wkup_padconf_array_essential[] = {
-
- {SR_PMIC_SCL, (PTU | IEN | M0)}, /* SR_PMIC_SCL */
- {SR_PMIC_SDA, (PTU | IEN | M0)}, /* SR_PMIC_SDA */
- {SYS_32K, (IEN | M0)}, /* SYS_32K */
- {FREF_CLK1_OUT, (PTD | IEN | M0)}, /* FREF_CLK1_OUT */
-
-};
-
-#endif /* _EVM4430_MUX_DATA_H */
diff --git a/cmd/tpm_test.c b/cmd/tpm_test.c
index b35eae8..c4ed8e5 100644
--- a/cmd/tpm_test.c
+++ b/cmd/tpm_test.c
@@ -471,6 +471,7 @@
break;
case TPM_MAXNVWRITES:
assert(i >= TPM_MAX_NV_WRITES_NOOWNER);
+ break;
default:
pr_err("\tunexpected error code %d (0x%x)\n",
result, result);
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 7bb878f..a402ffa 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -47,7 +47,6 @@
CONFIG_BAT2_LENGTH_8_MBYTES=y
CONFIG_BAT2_ACCESS_RW=y
CONFIG_BAT2_ICACHE_INHIBITED=y
-CONFIG_BAT2_ICACHE_GUARDED=y
CONFIG_BAT2_DCACHE_INHIBITED=y
CONFIG_BAT2_DCACHE_GUARDED=y
CONFIG_BAT2_USER_MODE_VALID=y
@@ -57,7 +56,6 @@
CONFIG_BAT3_BASE=0xF0000000
CONFIG_BAT3_ACCESS_RW=y
CONFIG_BAT3_ICACHE_INHIBITED=y
-CONFIG_BAT3_ICACHE_GUARDED=y
CONFIG_BAT3_DCACHE_INHIBITED=y
CONFIG_BAT3_DCACHE_GUARDED=y
CONFIG_BAT3_USER_MODE_VALID=y
@@ -93,7 +91,6 @@
CONFIG_BAT7_LENGTH_256_MBYTES=y
CONFIG_BAT7_ACCESS_RW=y
CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
CONFIG_BAT7_DCACHE_INHIBITED=y
CONFIG_BAT7_DCACHE_GUARDED=y
CONFIG_BAT7_USER_MODE_VALID=y
diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index b75cae6..bb705a1 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -169,3 +169,6 @@
CONFIG_USB_GADGET_PRODUCT_NUM=0x6165
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_TI_SCI=y
diff --git a/configs/bcmns_defconfig b/configs/bcmns_defconfig
new file mode 100644
index 0000000..02e2fbe
--- /dev/null
+++ b/configs/bcmns_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS=y
+CONFIG_TEXT_BASE=0x00008000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="ns-board"
+CONFIG_IDENT_STRING="Broadcom Northstar"
+CONFIG_SYS_LOAD_ADDR=0x00008000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000
+# CONFIG_BOOTSTD is not set
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n"
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl"
+CONFIG_SYS_PROMPT="northstar> "
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_SEAMA=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="NS"
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_NAND=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+# CONFIG_NET is not set
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index 5e01593..3d66313 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -34,7 +34,6 @@
CONFIG_BAT1_LENGTH_8_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/hc2910_2aghd05_defconfig b/configs/hc2910_2aghd05_defconfig
new file mode 100644
index 0000000..dfd3e65
--- /dev/null
+++ b/configs/hc2910_2aghd05_defconfig
@@ -0,0 +1,50 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_HISTB=y
+CONFIG_TEXT_BASE=0x00000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x1F0000
+CONFIG_DEFAULT_DEVICE_TREE="hi3798mv200-hc2910-2aghd05"
+CONFIG_SYS_PROMPT="HC2910# "
+CONFIG_IDENT_STRING="HC2910"
+CONFIG_SYS_LOAD_ADDR=0x800000
+# CONFIG_EXPERT is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_SYS_PBSIZE=537
+CONFIG_CMD_BOOTDEV=y
+# CONFIG_BOOTM_PLAN9 is not set
+# CONFIG_BOOTM_RTEMS is not set
+# CONFIG_BOOTM_VXWORKS is not set
+CONFIG_CMD_NVEDIT_INFO=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_LSBLK=y
+CONFIG_CMD_MBR=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_CAT=y
+CONFIG_CMD_EROFS=y
+CONFIG_CMD_EXT4_WRITE=y
+# CONFIG_ISO_PARTITION is not set
+CONFIG_PARTITION_TYPE_GUID=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+# CONFIG_NET is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+CONFIG_MMC_DW=y
+CONFIG_MMC_DW_K3=y
+# CONFIG_POWER is not set
+CONFIG_FS_BTRFS=y
+CONFIG_FAT_WRITE=y
+CONFIG_REGEX=y
+# CONFIG_EFI_LOADER is not set
diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig
index fa5ea2a..058e331 100644
--- a/configs/j7200_evm_a72_defconfig
+++ b/configs/j7200_evm_a72_defconfig
@@ -34,7 +34,7 @@
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_kern_${boot}; run get_fdt_${boot}; run get_overlay_${boot}; run run_kern"
CONFIG_LOGLEVEL=7
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index a8e48f8..0de6ae0 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -27,7 +27,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -38,7 +37,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
@@ -95,7 +93,6 @@
CONFIG_BAT7_LENGTH_256_MBYTES=y
CONFIG_BAT7_ACCESS_RW=y
CONFIG_BAT7_ICACHE_INHIBITED=y
-CONFIG_BAT7_ICACHE_GUARDED=y
CONFIG_BAT7_DCACHE_INHIBITED=y
CONFIG_BAT7_DCACHE_GUARDED=y
CONFIG_BAT7_USER_MODE_VALID=y
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index da72298..568e55f 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -28,7 +28,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -39,7 +38,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 41d0d2e..facd686 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -22,7 +22,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -33,7 +32,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 538a37b..c00e626 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -22,7 +22,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -33,7 +32,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index a2ad34d..8122124 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -22,7 +22,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -33,7 +32,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig
index 2d4876f..5b76512 100644
--- a/configs/mt7986a_bpir3_emmc_defconfig
+++ b/configs/mt7986a_bpir3_emmc_defconfig
@@ -7,15 +7,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb"
-CONFIG_SYS_PROMPT="MT7986> "
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc"
+CONFIG_SYS_PROMPT="BPI-R3> "
CONFIG_TARGET_MT7986=y
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
-CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb"
+CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-emmc"
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_CBSIZE=512
diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig
index 08edfe7..36547db 100644
--- a/configs/mt7986a_bpir3_sd_defconfig
+++ b/configs/mt7986a_bpir3_sd_defconfig
@@ -7,15 +7,15 @@
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x80000
CONFIG_ENV_OFFSET=0x300000
-CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb"
-CONFIG_SYS_PROMPT="MT7986> "
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd"
+CONFIG_SYS_PROMPT="BPI-R3> "
CONFIG_TARGET_MT7986=y
CONFIG_DEBUG_UART_BASE=0x11002000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x46000000
CONFIG_DEBUG_UART=y
# CONFIG_AUTOBOOT is not set
-CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb"
+CONFIG_DEFAULT_FDT_FILE="mt7986a-bpi-r3-sd"
CONFIG_LOGLEVEL=7
CONFIG_LOG=y
CONFIG_SYS_CBSIZE=512
diff --git a/configs/omap5_uevm_defconfig b/configs/omap5_uevm_defconfig
deleted file mode 100644
index c1ac60e..0000000
--- a/configs/omap5_uevm_defconfig
+++ /dev/null
@@ -1,72 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_SYS_MALLOC_F_LEN=0x4000
-CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
-CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00
-CONFIG_DEFAULT_DEVICE_TREE="omap5-uevm"
-CONFIG_SPL_TEXT_BASE=0x40300000
-CONFIG_OMAP54XX=y
-CONFIG_TARGET_OMAP5_UEVM=y
-CONFIG_OMAP_PLATFORM_RESET_TIME_MAX_USEC=16296
-CONFIG_SPL=y
-CONFIG_ENV_OFFSET_REDUND=0x280000
-CONFIG_ARMV7_LPAE=y
-CONFIG_AHCI=y
-CONFIG_DISTRO_DEFAULTS=y
-CONFIG_BOOTCOMMAND="if test ${dofastboot} -eq 1; then echo Boot fastboot requested, resetting dofastboot ...;setenv dofastboot 0; saveenv;echo Booting into fastboot ...; fastboot 1;fi;if test ${boot_fit} -eq 1; then run update_to_fit;fi;run findfdt; run finduuid; run distro_bootcmd;run emmc_android_boot; "
-CONFIG_DEFAULT_FDT_FILE="omap5-uevm.dtb"
-CONFIG_SYS_CONSOLE_INFO_QUIET=y
-CONFIG_SPL_MAX_SIZE=0x1dc00
-CONFIG_SYS_SPL_MALLOC=y
-CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
-# CONFIG_SPL_NAND_SUPPORT is not set
-CONFIG_SPL_OS_BOOT=y
-CONFIG_SPL_FALCON_BOOT_MMCSD=y
-CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500
-CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200
-CONFIG_SYS_MAXARGS=64
-CONFIG_CMD_SPL=y
-CONFIG_CMD_ASKENV=y
-CONFIG_CMD_DFU=y
-CONFIG_CMD_GPIO=y
-CONFIG_CMD_GPT=y
-CONFIG_CMD_I2C=y
-CONFIG_CMD_MMC=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_EXT4_WRITE=y
-CONFIG_OF_CONTROL=y
-CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
-CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_DEV=1
-CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
-CONFIG_VERSION_VARIABLE=y
-CONFIG_SCSI_AHCI=y
-CONFIG_DFU_MMC=y
-CONFIG_DFU_RAM=y
-CONFIG_TCA642X=y
-CONFIG_SYS_I2C_LEGACY=y
-CONFIG_SPL_SYS_I2C_LEGACY=y
-CONFIG_SUPPORT_EMMC_BOOT=y
-CONFIG_MMC_OMAP_HS=y
-CONFIG_HSMMC2_8BIT=y
-CONFIG_PALMAS_POWER=y
-CONFIG_SCSI=y
-CONFIG_SCSI_AHCI_PLAT=y
-CONFIG_CONS_INDEX=3
-CONFIG_SYS_NS16550_SERIAL=y
-CONFIG_USB=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_OMAP=y
-CONFIG_USB_DWC3_PHY_OMAP=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
-CONFIG_USB_GADGET_VENDOR_NUM=0x0403
-CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
-CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig
index 3d96e0a..5b85ce5 100644
--- a/configs/starqltechn_defconfig
+++ b/configs/starqltechn_defconfig
@@ -17,18 +17,24 @@
CONFIG_SYS_MAXARGS=64
CONFIG_SYS_CBSIZE=512
CONFIG_SYS_PBSIZE=532
+CONFIG_CMD_BOOTMENU=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_BMP=y
# CONFIG_NET is not set
+CONFIG_BUTTON=y
CONFIG_CLK=y
CONFIG_MSM_GPIO=y
CONFIG_QCOM_PMIC_GPIO=y
+CONFIG_DM_KEYBOARD=y
+CONFIG_BUTTON_KEYBOARD=y
CONFIG_PINCTRL=y
CONFIG_DM_PMIC=y
CONFIG_PMIC_QCOM=y
CONFIG_MSM_GENI_SERIAL=y
CONFIG_SPMI_MSM=y
CONFIG_VIDEO=y
+# CONFIG_VIDEO_FONT_8X16 is not set
+CONFIG_VIDEO_FONT_16X32=y
CONFIG_SYS_WHITE_ON_BLACK=y
CONFIG_VIDEO_SIMPLE=y
CONFIG_VIDEO_DT_SIMPLEFB=y
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 8e5f1c6..c10b5c2 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -22,7 +22,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -33,7 +32,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index f7f20ae..f61fb96 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -22,7 +22,6 @@
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_INHIBITED=y
-CONFIG_BAT0_ICACHE_GUARDED=y
CONFIG_BAT0_DCACHE_INHIBITED=y
CONFIG_BAT0_DCACHE_GUARDED=y
CONFIG_BAT0_USER_MODE_VALID=y
@@ -33,7 +32,6 @@
CONFIG_BAT1_LENGTH_4_MBYTES=y
CONFIG_BAT1_ACCESS_RW=y
CONFIG_BAT1_ICACHE_INHIBITED=y
-CONFIG_BAT1_ICACHE_GUARDED=y
CONFIG_BAT1_DCACHE_INHIBITED=y
CONFIG_BAT1_DCACHE_GUARDED=y
CONFIG_BAT1_USER_MODE_VALID=y
diff --git a/doc/board/broadcom/index.rst b/doc/board/broadcom/index.rst
index a56bd1f..ca34afc 100644
--- a/doc/board/broadcom/index.rst
+++ b/doc/board/broadcom/index.rst
@@ -9,3 +9,4 @@
bcm7xxx
raspberrypi
+ northstar
diff --git a/doc/board/broadcom/northstar.rst b/doc/board/broadcom/northstar.rst
new file mode 100644
index 0000000..f4bc0ac
--- /dev/null
+++ b/doc/board/broadcom/northstar.rst
@@ -0,0 +1,44 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+
+Broadcom Northstar Boards
+=========================
+
+This document describes how to use U-Boot on the Broadcom Northstar
+boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These
+were introduced in 2012-2013 and some of them are also called StrataGX.
+
+Northstar is part of the iProc SoC family.
+
+A good overview of these boards can be found in Jon Mason's presentation
+"Enabling New Hardware in U-Boot" where the difference between Northstar
+and Northstar Plus and Northstar 2 (Aarch64) is addressed.
+
+The ROM in the Northstar SoC will typically look into NOR flash memory
+for a boot loader, and the way this works is undocumented. It should be
+possible to execute U-Boot as the first binary from the NOR flash but
+this usage path is unexplored. Please add information if you know more.
+
+D-Link Boards
+-------------
+
+When we use U-Boot with D-Link routers, the NOR flash has a boot loader
+and web server that can re-flash the bigger NAND flash memory for object
+code in the SEAMA format, so on these platforms U-Boot is converted into
+a SEAMA binary and installed in the SoC using the flash tool resident in
+the NOR flash. Details can be found in the OpenWrt project codebase.
+
+Configure
+---------
+
+.. code-block:: console
+
+ $ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig
+
+Build
+-----
+
+.. code-block:: console
+
+ $ make CROSS_COMPILE=${CROSS_COMPILE}
+ $ ${CROSS_COMPILE}strip u-boot
diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
index bbb40b0..0cb71d9 100644
--- a/doc/board/qualcomm/qcs404.rst
+++ b/doc/board/qualcomm/qcs404.rst
@@ -9,8 +9,8 @@
This document describes the information about Qualcomm QCS404 evaluation board
and it's usage steps.
-U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
-It is loaded as an Android boot image through ABL
+The current boot flow support loading u-boot as an Android boot image via
+Qualcomm's UEFI-based ABL (Android) Bootloader.
Installation
------------
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index 8ef4749..71879c2 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -12,8 +12,8 @@
SDM845 - hi-end qualcomm chip, introduced in late 2017.
Mostly used in flagship phones and tablets of 2018.
-U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
-It is loaded as an Android boot image through ABL
+The current boot flow support loading u-boot as an Android boot image via
+Qualcomm's UEFI-based ABL (Android) Bootloader.
Installation
------------
diff --git a/doc/device-tree-bindings/serial/msm-geni-serial.txt b/doc/device-tree-bindings/serial/msm-geni-serial.txt
index 9eadc25..eaa39c9 100644
--- a/doc/device-tree-bindings/serial/msm-geni-serial.txt
+++ b/doc/device-tree-bindings/serial/msm-geni-serial.txt
@@ -1,6 +1,6 @@
Qualcomm GENI UART
Required properties:
-- compatible: must be "qcom,msm-geni-uart"
+- compatible: must be "qcom,geni-debug-uart"
- reg: start address and size of the registers
- clock: interface clock (must accept baudrate as a frequency)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 9101e53..75937fb 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -36,6 +36,8 @@
source "drivers/dma/Kconfig"
+source "drivers/extcon/Kconfig"
+
source "drivers/fastboot/Kconfig"
source "drivers/firmware/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index 58be410..ed1e71c 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -9,6 +9,7 @@
obj-$(CONFIG_$(SPL_TPL_)DMA) += dma/
obj-$(CONFIG_$(SPL_TPL_)DMA_LEGACY) += dma/
obj-$(CONFIG_$(SPL_TPL_)DFU) += dfu/
+obj-$(CONFIG_$(SPL_TPL_)EXTCON) += extcon/
obj-$(CONFIG_$(SPL_TPL_)GPIO) += gpio/
obj-$(CONFIG_$(SPL_TPL_)DRIVERS_MISC) += misc/
obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset/
diff --git a/drivers/extcon/Kconfig b/drivers/extcon/Kconfig
new file mode 100644
index 0000000..fbb7335
--- /dev/null
+++ b/drivers/extcon/Kconfig
@@ -0,0 +1,31 @@
+menu "Extcon Support"
+
+config EXTCON
+ bool "External Connector Class (extcon) support"
+ depends on DM
+ help
+ Say Y here to enable external connector class (extcon) support.
+ This allows monitoring external connectors and supports external
+ connectors with multiple states; i.e., an extcon that may have
+ multiple cables attached. For example, an external connector
+ of a device may be used to connect an HDMI cable and a AC adaptor,
+ and to host USB ports. Many of 30-pin connectors including PDMI
+ are also good examples.
+
+config EXTCON_SANDBOX
+ bool "Sandbox extcon"
+ depends on EXTCON
+ help
+ Enable extcon support for sandbox. This is an emulation of a real
+ extcon. Currectly all configuration is done in the probe.
+
+config EXTCON_MAX14526
+ bool "Maxim MAX14526 EXTCON Support"
+ depends on DM_I2C
+ depends on EXTCON
+ help
+ If you say yes here you get support for the MUIC device of
+ Maxim MAX14526. The MAX14526 MUIC is a USB port accessory
+ detector and switch.
+
+endmenu
diff --git a/drivers/extcon/Makefile b/drivers/extcon/Makefile
new file mode 100644
index 0000000..3309f2a
--- /dev/null
+++ b/drivers/extcon/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+
+obj-$(CONFIG_EXTCON) += extcon-uclass.o
+obj-$(CONFIG_EXTCON_SANDBOX) += extcon-sandbox.o
+obj-$(CONFIG_EXTCON_MAX14526) += extcon-max14526.o
diff --git a/drivers/extcon/extcon-max14526.c b/drivers/extcon/extcon-max14526.c
new file mode 100644
index 0000000..a33b5ef
--- /dev/null
+++ b/drivers/extcon/extcon-max14526.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <i2c.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <log.h>
+#include <extcon.h>
+#include <asm/gpio.h>
+
+#define CONTROL_1 0x01
+#define SW_CONTROL 0x03
+
+#define ID_200 0x10
+#define ADC_EN 0x02
+#define CP_EN 0x01
+
+#define DP_USB 0x00
+#define DP_UART 0x08
+#define DP_AUDIO 0x10
+#define DP_OPEN 0x38
+
+#define DM_USB 0x00
+#define DM_UART 0x01
+#define DM_AUDIO 0x02
+#define DM_OPEN 0x07
+
+#define AP_USB BIT(0)
+#define CP_USB BIT(1)
+#define CP_UART BIT(2)
+
+struct max14526_priv {
+ struct gpio_desc usif_gpio;
+ struct gpio_desc dp2t_gpio;
+ struct gpio_desc ifx_usb_vbus_gpio;
+};
+
+static void max14526_set_mode(struct udevice *dev, int mode)
+{
+ struct max14526_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ if ((mode & AP_USB) || (mode & CP_USB)) {
+ /* Connect CP UART signals to AP */
+ ret = dm_gpio_set_value(&priv->usif_gpio, 0);
+ if (ret)
+ log_debug("cp-uart > ap failed (%d)\n", ret);
+ }
+
+ if (mode & CP_UART) {
+ /* Connect CP UART signals to DP2T */
+ ret = dm_gpio_set_value(&priv->usif_gpio, 1);
+ if (ret)
+ log_debug("cp-uart > dp2t failed (%d)\n", ret);
+ }
+
+ if (mode & CP_USB) {
+ /* Connect CP USB to MUIC UART */
+ ret = dm_gpio_set_value(&priv->ifx_usb_vbus_gpio, 1);
+ if (ret)
+ log_debug("usb-vbus-gpio enable failed (%d)\n", ret);
+
+ ret = dm_gpio_set_value(&priv->dp2t_gpio, 1);
+ if (ret)
+ log_debug("cp-usb > muic-uart failed (%d)\n", ret);
+ }
+
+ if ((mode & AP_USB) || (mode & CP_UART)) {
+ /* Connect CP UART to MUIC UART */
+ ret = dm_gpio_set_value(&priv->dp2t_gpio, 0);
+ if (ret)
+ log_debug("cp-uart > muic-uart failed (%d)\n", ret);
+ }
+
+ if (mode & AP_USB) {
+ /* Enables USB Path */
+ ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_USB | DM_USB);
+ if (ret)
+ log_debug("USB path set failed: %d\n", ret);
+ }
+
+ if ((mode & CP_USB) || (mode & CP_UART)) {
+ /* Enables UART Path */
+ ret = dm_i2c_reg_write(dev, SW_CONTROL, DP_UART | DM_UART);
+ if (ret)
+ log_debug("UART path set failed: %d\n", ret);
+ }
+
+ /* Enables 200K, Charger Pump, and ADC */
+ ret = dm_i2c_reg_write(dev, CONTROL_1, ID_200 | ADC_EN | CP_EN);
+ if (ret)
+ log_debug("200K, Charger Pump, and ADC set failed: %d\n", ret);
+}
+
+static int max14526_probe(struct udevice *dev)
+{
+ struct max14526_priv *priv = dev_get_priv(dev);
+ int ret, mode = 0;
+
+ ret = gpio_request_by_name(dev, "usif-gpios", 0,
+ &priv->usif_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_err("could not decode usif-gpios (%d)\n", ret);
+ return ret;
+ }
+
+ ret = gpio_request_by_name(dev, "dp2t-gpios", 0,
+ &priv->dp2t_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_err("could not decode dp2t-gpios (%d)\n", ret);
+ return ret;
+ }
+
+ if (dev_read_bool(dev, "maxim,ap-usb"))
+ mode |= AP_USB;
+
+ if (dev_read_bool(dev, "maxim,cp-usb")) {
+ mode |= CP_USB;
+
+ ret = gpio_request_by_name(dev, "usb-vbus-gpios", 0,
+ &priv->ifx_usb_vbus_gpio, GPIOD_IS_OUT);
+ if (ret) {
+ log_err("could not decode usb-vbus-gpios (%d)\n", ret);
+ return ret;
+ }
+ }
+
+ if (dev_read_bool(dev, "maxim,cp-uart"))
+ mode |= CP_UART;
+
+ max14526_set_mode(dev, mode);
+
+ return 0;
+}
+
+static const struct udevice_id max14526_ids[] = {
+ { .compatible = "maxim,max14526-muic" },
+ { }
+};
+
+U_BOOT_DRIVER(extcon_max14526) = {
+ .name = "extcon_max14526",
+ .id = UCLASS_EXTCON,
+ .of_match = max14526_ids,
+ .probe = max14526_probe,
+ .priv_auto = sizeof(struct max14526_priv),
+};
diff --git a/drivers/extcon/extcon-sandbox.c b/drivers/extcon/extcon-sandbox.c
new file mode 100644
index 0000000..ab6a6c1
--- /dev/null
+++ b/drivers/extcon/extcon-sandbox.c
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+
+static const struct udevice_id sandbox_extcon_ids[] = {
+ { .compatible = "sandbox,extcon" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(extcon_sandbox) = {
+ .name = "extcon_sandbox",
+ .id = UCLASS_EXTCON,
+ .of_match = sandbox_extcon_ids,
+};
diff --git a/drivers/extcon/extcon-uclass.c b/drivers/extcon/extcon-uclass.c
new file mode 100644
index 0000000..9dd22b5
--- /dev/null
+++ b/drivers/extcon/extcon-uclass.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#define LOG_CATEGORY UCLASS_EXTCON
+
+#include <common.h>
+#include <extcon.h>
+#include <dm.h>
+
+UCLASS_DRIVER(extcon) = {
+ .id = UCLASS_EXTCON,
+ .name = "extcon",
+ .per_device_plat_auto = sizeof(struct extcon_uc_plat),
+};
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 4e1ae03..04460f1 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -511,6 +511,13 @@
legacy UART or other devices in the Winbond Super IO chips
on X86 platforms.
+config QCOM_GENI_SE
+ bool "Qualcomm GENI Serial Engine Driver"
+ depends on ARCH_SNAPDRAGON
+ help
+ The driver manages Generic Interface (GENI) firmware based
+ Qualcomm Technologies, Inc. Universal Peripheral (QUP) Wrapper.
+
config QFW
bool
help
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3b792f2..52aed09 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -60,6 +60,7 @@
obj-$(CONFIG_P2SB) += p2sb-uclass.o
obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
+obj-$(CONFIG_QCOM_GENI_SE) += qcom-geni-se.o
ifdef CONFIG_QFW
obj-y += qfw.o
obj-$(CONFIG_QFW_PIO) += qfw_pio.o
diff --git a/drivers/misc/qcom-geni-se.c b/drivers/misc/qcom-geni-se.c
new file mode 100644
index 0000000..281a5ec
--- /dev/null
+++ b/drivers/misc/qcom-geni-se.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Generic Interface (GENI) Serial Engine (SE) Wrapper
+ *
+ * Copyright (C) 2023 Linaro Ltd. <vladimir.zapolskiy@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <misc.h>
+#include <asm/io.h>
+
+static int geni_se_qup_read(struct udevice *dev, int offset,
+ void *buf, int size)
+{
+ fdt_addr_t base = dev_read_addr(dev);
+
+ if (size != sizeof(u32))
+ return -EINVAL;
+
+ *(u32 *)buf = readl(base + offset);
+
+ return size;
+}
+
+static struct misc_ops geni_se_qup_ops = {
+ .read = geni_se_qup_read,
+};
+
+static const struct udevice_id geni_se_qup_ids[] = {
+ { .compatible = "qcom,geni-se-qup" },
+ {}
+};
+
+U_BOOT_DRIVER(geni_se_qup) = {
+ .name = "geni_se_qup",
+ .id = UCLASS_MISC,
+ .of_match = geni_se_qup_ids,
+ .ops = &geni_se_qup_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c
index 2cec5b9..71962cd 100644
--- a/drivers/mmc/hi6220_dw_mmc.c
+++ b/drivers/mmc/hi6220_dw_mmc.c
@@ -100,6 +100,8 @@
.data = (ulong)&hi6220_mmc_data },
{ .compatible = "hisilicon,hi3798cv200-dw-mshc",
.data = (ulong)&hi6220_mmc_data },
+ { .compatible = "hisilicon,hi3798mv200-dw-mshc",
+ .data = (ulong)&hi6220_mmc_data },
{ .compatible = "hisilicon,hi3660-dw-mshc",
.data = (ulong)&hi3660_mmc_data },
{ }
diff --git a/drivers/pci/pci_auto.c b/drivers/pci/pci_auto.c
index 14fd3bb..0123036 100644
--- a/drivers/pci/pci_auto.c
+++ b/drivers/pci/pci_auto.c
@@ -580,10 +580,6 @@
break;
#endif
- case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
- debug("PCI AutoConfig: Found PowerPC device\n");
- /* fall through */
-
default:
dm_pciauto_setup_device(dev, pci_mem, pci_prefetch, pci_io);
break;
diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index 8a81a74..249cfe6 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -22,10 +22,33 @@
struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
u32 addr;
- addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+ if (offset > 0xff) {
+ *value = pci_get_ff(size);
+ return 0;
+ }
+
+ /* Skip mpc85xx PCI controller's ATMU inbound registers */
+ if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5) {
+ *value = 0;
+ return 0;
+ }
+
+ addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
- *value = pci_conv_32_to_size(in_le32(priv->cfg_data), offset, size);
+
+ switch (size) {
+ case PCI_SIZE_8:
+ *value = in_8(priv->cfg_data + (offset & 3));
+ break;
+ case PCI_SIZE_16:
+ *value = in_le16(priv->cfg_data + (offset & 2));
+ break;
+ case PCI_SIZE_32:
+ *value = in_le32(priv->cfg_data);
+ break;
+ }
return 0;
}
@@ -37,10 +60,30 @@
struct mpc85xx_pci_priv *priv = dev_get_priv(dev);
u32 addr;
- addr = PCI_CONF1_EXT_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
+ if (offset > 0xff)
+ return 0;
+
+ /* Skip mpc85xx PCI controller's ATMU inbound registers */
+ if (PCI_BUS(bdf) == 0 && PCI_DEV(bdf) == 0 && PCI_FUNC(bdf) == 0 &&
+ (offset & ~3) >= PCI_BASE_ADDRESS_0 && (offset & ~3) <= PCI_BASE_ADDRESS_5)
+ return 0;
+
+ addr = PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset);
out_be32(priv->cfg_addr, addr);
sync();
- out_le32(priv->cfg_data, pci_conv_size_to_32(0, value, offset, size));
+
+ switch (size) {
+ case PCI_SIZE_8:
+ out_8(priv->cfg_data + (offset & 3), value);
+ break;
+ case PCI_SIZE_16:
+ out_le16(priv->cfg_data + (offset & 2), value);
+ break;
+ case PCI_SIZE_32:
+ out_le32(priv->cfg_data, value);
+ break;
+ }
+ sync();
return 0;
}
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 47e2d67..5a4d58b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -349,10 +349,10 @@
{
int err;
- /* try pupd_r1_r0 if pullen_pullsel return error */
+ /* set pupd_r1_r0 if pullen_pullsel succeeded */
err = mtk_pinconf_bias_set_pullen_pullsel(dev, pin, disable, pullup,
val);
- if (err)
+ if (!err)
return mtk_pinconf_bias_set_pupd_r1_r0(dev, pin, disable,
pullup, val);
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 10d07da..7faf678 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -946,6 +946,8 @@
config MSM_GENI_SERIAL
bool "Qualcomm on-chip GENI UART"
+ select MISC
+ imply QCOM_GENI_SE
help
Support UART based on Generic Interface (GENI) Serial Engine (SE),
used on Qualcomm Snapdragon SoCs. Should support all qualcomm SOCs
diff --git a/drivers/serial/serial_msm_geni.c b/drivers/serial/serial_msm_geni.c
index 3943ca4..78fd938 100644
--- a/drivers/serial/serial_msm_geni.c
+++ b/drivers/serial/serial_msm_geni.c
@@ -11,15 +11,10 @@
#include <clk.h>
#include <common.h>
#include <dm.h>
-#include <dm/pinctrl.h>
#include <errno.h>
-#include <linux/compiler.h>
-#include <log.h>
#include <linux/delay.h>
-#include <malloc.h>
+#include <misc.h>
#include <serial.h>
-#include <watchdog.h>
-#include <linux/bug.h>
#define UART_OVERSAMPLING 32
#define STALE_TIMEOUT 160
@@ -116,6 +111,10 @@
#define TX_FIFO_DEPTH_MSK (GENMASK(21, 16))
#define TX_FIFO_DEPTH_SHFT 16
+/* GENI SE QUP Registers */
+#define QUP_HW_VER_REG 0x4
+#define QUP_SE_VERSION_2_5 0x20050000
+
/*
* Predefined packing configuration of the serial engine (CFG0, CFG1 regs)
* for uart mode.
@@ -133,11 +132,12 @@
struct msm_serial_data {
phys_addr_t base;
u32 baud;
+ u32 oversampling;
};
unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
- 32000000, 48000000, 64000000, 80000000,
- 96000000, 100000000};
+ 32000000, 48000000, 64000000, 80000000,
+ 96000000, 100000000};
/**
* get_clk_cfg() - Get clock rate to apply on clock supplier.
@@ -166,8 +166,7 @@
*
* Return: frequency, supported by clock supplier, multiple of clk_freq.
*/
-static int get_clk_div_rate(u32 baud,
- u64 sampling_rate, u32 *clk_div)
+static int get_clk_div_rate(u32 baud, u64 sampling_rate, u32 *clk_div)
{
unsigned long ser_clk;
unsigned long desired_clk;
@@ -189,7 +188,7 @@
struct clk *clk;
int ret;
- clk = devm_clk_get(dev, "se-clk");
+ clk = devm_clk_get(dev, NULL);
if (!clk)
return -EINVAL;
@@ -234,7 +233,7 @@
}
static inline void geni_serial_baud(phys_addr_t base_address, u32 clk_div,
- int baud)
+ int baud)
{
u32 s_clk_cfg = 0;
@@ -245,15 +244,15 @@
writel(s_clk_cfg, base_address + GENI_SER_S_CLK_CFG);
}
-int msm_serial_setbrg(struct udevice *dev, int baud)
+static int msm_serial_setbrg(struct udevice *dev, int baud)
{
struct msm_serial_data *priv = dev_get_priv(dev);
+ u64 clk_rate;
+ u32 clk_div;
priv->baud = baud;
- u32 clk_div;
- u64 clk_rate;
- clk_rate = get_clk_div_rate(baud, UART_OVERSAMPLING, &clk_div);
+ clk_rate = get_clk_div_rate(baud, priv->oversampling, &clk_div);
geni_serial_set_clock_rate(dev, clk_rate);
geni_serial_baud(priv->base, clk_div, baud);
@@ -274,7 +273,7 @@
* reached.
*/
static bool qcom_geni_serial_poll_bit(const struct udevice *dev, int offset,
- int field, bool set)
+ int field, bool set)
{
u32 reg;
struct msm_serial_data *priv = dev_get_priv(dev);
@@ -487,6 +486,31 @@
.setbrg = msm_serial_setbrg,
};
+static void geni_set_oversampling(struct udevice *dev)
+{
+ struct msm_serial_data *priv = dev_get_priv(dev);
+ struct udevice *parent_dev = dev_get_parent(dev);
+ u32 geni_se_version;
+ int ret;
+
+ priv->oversampling = UART_OVERSAMPLING;
+
+ /*
+ * It could happen that GENI SE IP is missing in the board's device
+ * tree or GENI UART node is a direct child of SoC device tree node.
+ */
+ if (device_get_uclass_id(parent_dev) != UCLASS_MISC)
+ return;
+
+ ret = misc_read(parent_dev, QUP_HW_VER_REG,
+ &geni_se_version, sizeof(geni_se_version));
+ if (ret != sizeof(geni_se_version))
+ return;
+
+ if (geni_se_version >= QUP_SE_VERSION_2_5)
+ priv->oversampling /= 2;
+}
+
static inline void geni_serial_init(struct udevice *dev)
{
struct msm_serial_data *priv = dev_get_priv(dev);
@@ -530,6 +554,8 @@
{
struct msm_serial_data *priv = dev_get_priv(dev);
+ geni_set_oversampling(dev);
+
/* No need to reinitialize the UART after relocation */
if (gd->flags & GD_FLG_RELOC)
return 0;
@@ -554,7 +580,9 @@
}
static const struct udevice_id msm_serial_ids[] = {
- {.compatible = "qcom,msm-geni-uart"}, {}};
+ { .compatible = "qcom,geni-debug-uart" },
+ { }
+};
U_BOOT_DRIVER(serial_msm_geni) = {
.name = "serial_msm_geni",
@@ -564,6 +592,7 @@
.priv_auto = sizeof(struct msm_serial_data),
.probe = msm_serial_probe,
.ops = &msm_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
};
#ifdef CONFIG_DEBUG_UART_MSM_GENI
diff --git a/include/configs/bcmns.h b/include/configs/bcmns.h
new file mode 100644
index 0000000..6f5f2b7
--- /dev/null
+++ b/include/configs/bcmns.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BCM_NS_H
+#define __BCM_NS_H
+
+#include <linux/sizes.h>
+
+/* Physical Memory Map */
+#define V2M_BASE 0x00000000
+#define PHYS_SDRAM_1 V2M_BASE
+
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Called "periph_clk" in Linux, used by the global timer */
+#define CFG_SYS_HZ_CLOCK 500000000
+
+/* Called "iprocslow" in Linux */
+#define CFG_SYS_NS16550_CLK 125000000
+
+/* console configuration */
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=2\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
+ " ${max_cpus} ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0"
+
+#define KERNEL_LOADADDR_CFG \
+ "loadaddr=0x01000000\0" \
+ "dtb_loadaddr=0x02000000\0"
+
+/*
+ * Hardcoded for the only boards we support, if you add more
+ * boards, add a more clever bootcmd!
+ */
+#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000"
+
+#define ARCH_ENV_SETTINGS \
+ CONSOLE_ARGS \
+ MAX_CPUS \
+ EXTRA_ARGS \
+ KERNEL_LOADADDR_CFG \
+ NS_BOOTCMD
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ ARCH_ENV_SETTINGS
+
+#endif /* __BCM_NS_H */
diff --git a/include/configs/hc2910-2aghd05.h b/include/configs/hc2910-2aghd05.h
new file mode 100644
index 0000000..3db9a47
--- /dev/null
+++ b/include/configs/hc2910-2aghd05.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __HC2910_2AGHD05_CONFIG_H__
+#define __HC2910_2AGHD05_CONFIG_H__
+
+#endif
diff --git a/include/configs/omap5_uevm.h b/include/configs/omap5_uevm.h
deleted file mode 100644
index 39d0b40..0000000
--- a/include/configs/omap5_uevm.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * (C) Copyright 2013
- * Texas Instruments Incorporated.
- * Sricharan R <r.sricharan@ti.com>
- *
- * Configuration settings for the TI EVM5430 board.
- * See ti_omap5_common.h for omap5 common settings.
- */
-
-#ifndef __CONFIG_OMAP5_EVM_H
-#define __CONFIG_OMAP5_EVM_H
-
-#include <environment/ti/dfu.h>
-
-#ifndef CONFIG_SPL_BUILD
-/* Define the default GPT table for eMMC */
-#define PARTS_DEFAULT \
- "uuid_disk=${uuid_gpt_disk};" \
- "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}"
-#endif
-
-#define DFUARGS \
- "dfu_bufsiz=0x10000\0" \
- DFU_ALT_INFO_MMC \
- DFU_ALT_INFO_EMMC \
- DFU_ALT_INFO_RAM
-
-#include <configs/ti_omap5_common.h>
-
-#define CFG_SYS_NS16550_COM3 UART3_BASE
-
-/* MMC ENV related defines */
-
-/* Required support for the TCA642X GPIO we have on the uEVM */
-#define CFG_SYS_I2C_TCA642X_BUS_NUM 4
-#define CFG_SYS_I2C_TCA642X_ADDR 0x22
-
-/* Enabled commands */
-
-/* USB Networking options */
-
-#define CONSOLEDEV "ttyS2"
-
-#endif /* __CONFIG_OMAP5_EVM_H */
diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h
index 2211751..673268d 100644
--- a/include/configs/sdm845.h
+++ b/include/configs/sdm845.h
@@ -16,7 +16,7 @@
#define CFG_EXTRA_ENV_SETTINGS \
"bootm_size=0x4000000\0" \
"bootm_low=0x80000000\0" \
- "stdin=serial\0" \
+ "stdin=serial,button-kbd\0" \
"stdout=serial,vidconsole\0" \
"stderr=serial,vidconsole\0" \
"preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 5386c3fa..307ad69 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -56,6 +56,7 @@
UCLASS_EFI_MEDIA, /* Devices provided by UEFI firmware */
UCLASS_ETH, /* Ethernet device */
UCLASS_ETH_PHY, /* Ethernet PHY device */
+ UCLASS_EXTCON, /* External Connector Class */
UCLASS_FIRMWARE, /* Firmware */
UCLASS_FPGA, /* FPGA device */
UCLASS_FUZZING_ENGINE, /* Fuzzing engine */
diff --git a/include/dt-bindings/clock/bcm-nsp.h b/include/dt-bindings/clock/bcm-nsp.h
new file mode 100644
index 0000000..ad5827c
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-nsp.h
@@ -0,0 +1,51 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL 0
+#define BCM_NSP_GENPLL_PHY_CLK 1
+#define BCM_NSP_GENPLL_ENET_SW_CLK 2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
+#define BCM_NSP_GENPLL_SATA1_CLK 5
+#define BCM_NSP_GENPLL_SATA2_CLK 6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0 0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
+#define BCM_NSP_LCPLL0_SDIO_CLK 2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
+
+#endif /* _CLOCK_BCM_NSP_H */
diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h
index 136de247..8a05790 100644
--- a/include/dt-bindings/clock/histb-clock.h
+++ b/include/dt-bindings/clock/histb-clock.h
@@ -70,6 +70,18 @@
#define HISTB_USB3_UTMI_CLK1 48
#define HISTB_USB3_PIPE_CLK1 49
#define HISTB_USB3_SUSPEND_CLK1 50
+#define HISTB_SDIO1_BIU_CLK 51
+#define HISTB_SDIO1_CIU_CLK 52
+#define HISTB_SDIO1_DRV_CLK 53
+#define HISTB_SDIO1_SAMPLE_CLK 54
+
+/* Hi3798MV200 specific clocks */
+
+// reuse clocks of histb
+#define HI3798MV200_GMAC_CLK HISTB_ETH0_MAC_CLK
+#define HI3798MV200_GMACIF_CLK HISTB_ETH0_MACIF_CLK
+#define HI3798MV200_FEMAC_CLK HISTB_ETH1_MAC_CLK
+#define HI3798MV200_FEMACIF_CLK HISTB_ETH1_MACIF_CLK
/* clocks provided by mcu CRG */
#define HISTB_MCE_CLK 1
diff --git a/include/extcon.h b/include/extcon.h
new file mode 100644
index 0000000..d060f5a
--- /dev/null
+++ b/include/extcon.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#ifndef __EXTCON_H
+#define __EXTCON_H
+
+struct udevice;
+
+/**
+ * struct extcon_uc_plat - Platform data the uclass stores about each device
+ *
+ * To be filled
+ */
+struct extcon_uc_plat {
+};
+
+#endif
diff --git a/test/dm/Makefile b/test/dm/Makefile
index c8534b5..3799b1a 100644
--- a/test/dm/Makefile
+++ b/test/dm/Makefile
@@ -49,6 +49,7 @@
obj-$(CONFIG_ECDSA_VERIFY) += ecdsa.o
obj-$(CONFIG_EFI_MEDIA_SANDBOX) += efi_media.o
obj-$(CONFIG_DM_ETH) += eth.o
+obj-$(CONFIG_EXTCON) += extcon.o
ifneq ($(CONFIG_EFI_PARTITION),)
obj-$(CONFIG_FASTBOOT_FLASH_MMC) += fastboot.o
endif
diff --git a/test/dm/extcon.c b/test/dm/extcon.c
new file mode 100644
index 0000000..6a4e22b
--- /dev/null
+++ b/test/dm/extcon.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2023 Svyatoslav Ryhel <clamor95@gmail.com>
+ */
+
+#include <dm.h>
+#include <dm/test.h>
+#include <extcon.h>
+#include <test/test.h>
+#include <test/ut.h>
+
+static int dm_test_extcon(struct unit_test_state *uts)
+{
+ struct udevice *dev;
+
+ ut_assertok(uclass_get_device_by_name(UCLASS_EXTCON, "extcon", &dev));
+
+ return 0;
+}
+
+DM_TEST(dm_test_extcon, UT_TESTF_SCAN_FDT);