commit 248c4faa9f0499971dadf148e666b087384117f0
author Bin Meng <bmeng.cn@gmail.com> Mon Feb 01 01:40:52 2016 -0800
committer Bin Meng <bmeng.cn@gmail.com> Fri Feb 05 12:47:22 2016 +0800
tree 3a65f3a2c335cd186828689b8c5abd4c3b784239
parent b46c2088da17b8f9210bf0860af88ec533435af9

x86: irq: Convert to use DM PCI API

Now that we have irq router's udevice passed as a parameter, it's
time to start using the DM PCI API instead of those legacy ones.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>

arch/x86/cpu/irq.c

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c
index fea6f65..295078305 100644
--- a/arch/x86/cpu/irq.c
+++ b/arch/x86/cpu/irq.c
@@ -25,7 +25,7 @@
 	int base = priv->link_base;
 
 	if (priv->config == PIRQ_VIA_PCI)
-		pirq = x86_pci_read_config8(priv->bdf, LINK_N2V(link, base));
+		dm_pci_read_config8(dev->parent, LINK_N2V(link, base), &pirq);
 	else
 		pirq = readb(priv->ibase + LINK_N2V(link, base));
 
@@ -55,7 +55,7 @@
 		return;
 
 	if (priv->config == PIRQ_VIA_PCI)
-		x86_pci_write_config8(priv->bdf, LINK_N2V(link, base), irq);
+		dm_pci_write_config8(dev->parent, LINK_N2V(link, base), irq);
 	else
 		writeb(irq, priv->ibase + LINK_N2V(link, base));
 }
@@ -138,7 +138,7 @@
 		 *   2) memory range decoding is enabled.
 		 * Hence we don't do any santify test here.
 		 */
-		priv->ibase = x86_pci_read_config32(priv->bdf, ibase_off);
+		dm_pci_read_config32(dev->parent, ibase_off, &priv->ibase);
 		priv->ibase &= ~0xf;
 	}
 

arch/x86/cpu/queensbay/irq.c

diff --git a/arch/x86/cpu/queensbay/irq.c b/arch/x86/cpu/queensbay/irq.c
index 44369f7..63d0f35 100644
--- a/arch/x86/cpu/queensbay/irq.c
+++ b/arch/x86/cpu/queensbay/irq.c
@@ -18,7 +18,7 @@
 	struct tnc_rcba *rcba;
 	u32 base;
 
-	base = x86_pci_read_config32(TNC_LPC, LPC_RCBA);
+	dm_pci_read_config32(dev->parent, LPC_RCBA, &base);
 	base &= ~MEM_BAR_EN;
 	rcba = (struct tnc_rcba *)base;