mpc83xx: Add support for the MPC832XEMDS board
This patch supports DUART, ETH3/4 and PCI etc.
Signed-off-by: Dave Liu <daveliu@freescale.com>
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index 1b51078..bc61219 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -92,6 +92,22 @@
case SPR_8360_REV12:
puts("MPC8360, ");
break;
+ case SPR_8323E_REV10:
+ case SPR_8323E_REV11:
+ puts("MPC8323E, ");
+ break;
+ case SPR_8323_REV10:
+ case SPR_8323_REV11:
+ puts("MPC8323, ");
+ break;
+ case SPR_8321E_REV10:
+ case SPR_8321E_REV11:
+ puts("MPC8321E, ");
+ break;
+ case SPR_8321_REV10:
+ case SPR_8321_REV11:
+ puts("MPC8321, ");
+ break;
default:
puts("Rev: Unknown\n");
return -1; /* Not sure what this is */
diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c
index 7574fab..eb256e5 100644
--- a/cpu/mpc83xx/cpu_init.c
+++ b/cpu/mpc83xx/cpu_init.c
@@ -119,6 +119,11 @@
#ifdef CFG_SICRL
im->sysconf.sicrl = CFG_SICRL;
#endif
+ /* DDR control driver register */
+#ifdef CFG_DDRCDR
+ im->sysconf.ddrcdr = CFG_DDRCDR;
+#endif
+
#ifdef CONFIG_QE
/* Config QE ioports */
config_qe_ioports();
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index 40ba6b0..9fd1bf1 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -107,15 +107,19 @@
#endif
u32 core_clk;
u32 i2c1_clk;
+#if !defined(CONFIG_MPC832X)
u32 i2c2_clk;
+#endif
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
u32 ddr_clk;
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
+ u32 ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
u32 qepmf;
u32 qepdf;
- u32 ddr_sec_clk;
u32 qe_clk;
u32 brg_clk;
#endif
@@ -227,10 +231,12 @@
return -9;
}
#endif
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
i2c1_clk = csb_clk;
#endif
+#if !defined(CONFIG_MPC832X)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
+#endif
switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
case 0:
@@ -249,12 +255,9 @@
/* unkown SCCR_ENCCM value */
return -6;
}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+
lbiu_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
-#else
-#error Unknown MPC83xx chip
-#endif
lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
switch (lcrr) {
case 2:
@@ -266,17 +269,14 @@
/* unknown lcrr */
return -10;
}
-#if defined(CONFIG_MPC8349) || defined(CONFIG_MPC8360)
+
ddr_clk = csb_clk *
(1 + ((im->reset.rcwl & HRCWL_DDRCM) >> HRCWL_DDRCM_SHIFT));
corepll = (im->reset.rcwl & HRCWL_COREPLL) >> HRCWL_COREPLL_SHIFT;
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
ddr_sec_clk = csb_clk * (1 +
((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
#endif
-#else
-#error Unknown MPC83xx chip
-#endif
corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
if (corecnf_tab_index > (sizeof(corecnf_tab) / sizeof(corecnf_t))) {
@@ -306,7 +306,7 @@
return -12;
}
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
qepmf = (im->reset.rcwl & HRCWL_CEPMF) >> HRCWL_CEPMF_SHIFT;
qepdf = (im->reset.rcwl & HRCWL_CEPDF) >> HRCWL_CEPDF_SHIFT;
qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
@@ -322,13 +322,17 @@
#endif
gd->core_clk = core_clk;
gd->i2c1_clk = i2c1_clk;
+#if !defined(CONFIG_MPC832X)
gd->i2c2_clk = i2c2_clk;
+#endif
gd->enc_clk = enc_clk;
gd->lbiu_clk = lbiu_clk;
gd->lclk_clk = lclk_clk;
gd->ddr_clk = ddr_clk;
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
gd->ddr_sec_clk = ddr_sec_clk;
+#endif
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
gd->qe_clk = qe_clk;
gd->brg_clk = brg_clk;
#endif
@@ -352,18 +356,21 @@
printf("Clock configuration:\n");
printf(" Coherent System Bus: %4d MHz\n", gd->csb_clk / 1000000);
printf(" Core: %4d MHz\n", gd->core_clk / 1000000);
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360) || defined(CONFIG_MPC832X)
printf(" QE: %4d MHz\n", gd->qe_clk / 1000000);
+ printf(" BRG: %4d MHz\n", gd->brg_clk / 1000000);
#endif
printf(" Local Bus Controller:%4d MHz\n", gd->lbiu_clk / 1000000);
printf(" Local Bus: %4d MHz\n", gd->lclk_clk / 1000000);
printf(" DDR: %4d MHz\n", gd->ddr_clk / 1000000);
-#if defined (CONFIG_MPC8360)
+#if defined(CONFIG_MPC8360)
printf(" DDR Secondary: %4d MHz\n", gd->ddr_sec_clk / 1000000);
#endif
printf(" SEC: %4d MHz\n", gd->enc_clk / 1000000);
printf(" I2C1: %4d MHz\n", gd->i2c1_clk / 1000000);
+#if !defined(CONFIG_MPC832X)
printf(" I2C2: %4d MHz\n", gd->i2c2_clk / 1000000);
+#endif
#if defined(CONFIG_MPC8349)
printf(" TSEC1: %4d MHz\n", gd->tsec1_clk / 1000000);
printf(" TSEC2: %4d MHz\n", gd->tsec2_clk / 1000000);