arm64: versal: fpga: Add PL bit stream load support
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 105a299..fe398a1 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -56,6 +56,15 @@
Enable FPGA driver for loading bitstream in BIT and BIN format
on Xilinx Zynq UltraScale+ (ZynqMP) device.
+config FPGA_VERSALPL
+ bool "Enable Xilinx FPGA driver for Versal"
+ depends on FPGA_XILINX
+ help
+ Enable FPGA driver for loading bitstream in PDI format on Xilinx
+ Versal device. PDI is a new programmable device image format for
+ Versal. The bitstream will only be generated as PDI for Versal
+ platform.
+
config FPGA_SPARTAN3
bool "Enable Spartan3 FPGA driver"
depends on FPGA_XILINX