arm64: versal: fpga: Add PL bit stream load support
This patch adds PL bitstream load support for Versal platform. The PL
bitstream is loaded by making an SMC to ATF which in turn communicates
with platform firmware which configures and loads PL bitstream on to PL.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c
index f513550..4b0334b 100644
--- a/drivers/fpga/xilinx.c
+++ b/drivers/fpga/xilinx.c
@@ -226,7 +226,10 @@
case xilinx_zynqmp:
printf("ZynqMP PL\n");
break;
- /* Add new family types here */
+ case xilinx_versal:
+ printf("Versal PL\n");
+ break;
+ /* Add new family types here */
default:
printf ("Unknown family type, %d\n", desc->family);
}
@@ -257,6 +260,9 @@
case csu_dma:
printf("csu_dma configuration interface (ZynqMP)\n");
break;
+ case cfi:
+ printf("CFI configuration interface (Versal)\n");
+ break;
/* Add new interface types here */
default:
printf ("Unsupported interface type, %d\n", desc->iface);