ram: k3-ddrss: Allow use of dt provided initial frequency
Allow device tree to provide ti,ddr-freq0 to be used as the initial DDR
frequency that is set for lpddr4 before initialization of the
controller. Make this optional and continue to use PLL bypass frequency
as is done currently if ti,ddr-freq0 is not provided.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index df3290a..1ea0a70 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -39,6 +39,8 @@
- reg: Must add "ss" to list if the above ss region is included.
- ti,ecc-enable: Boolean flag to enable ECC. This will reduce available DDR
by 1/9.
+- ti,ddr-freq0: Initial frequency set point, if not provided PLL bypass
+ frequency will be used.
Example (J721E):
================
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 6217f98..e8b7aec 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -134,6 +134,7 @@
struct power_domain ddrdata_pwrdmn;
struct clk ddr_clk;
struct clk osc_clk;
+ u32 ddr_freq0;
u32 ddr_freq1;
u32 ddr_freq2;
u32 ddr_fhs_cnt;
@@ -223,9 +224,7 @@
else if (req_type == 2)
clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq2);
else if (req_type == 0)
- /* Put DDR pll in bypass mode */
- clk_set_rate(&ddrss->ddr_clk,
- clk_get_rate(&ddrss->osc_clk));
+ clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
else
printf("%s: Invalid freq request type\n", __func__);
@@ -276,8 +275,7 @@
ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
break;
case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
- /* Set to bypass frequency for LPDDR4*/
- ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
+ ret = clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq0);
break;
default:
ret = -EINVAL;
@@ -394,6 +392,13 @@
ddrss->instance = 0;
}
+ ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0);
+ if (ret) {
+ ddrss->ddr_freq0 = clk_get_rate(&ddrss->osc_clk);
+ dev_dbg(dev,
+ "ddr freq0 not populated, using bypass frequency.\n");
+ }
+
ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1);
if (ret)
dev_err(dev, "ddr freq1 not populated %d\n", ret);