* Code cleanup
* Patch by Sascha Hauer, 28 Jun:
- add generic support for Motorola i.MX architecture
- add support for mx1ads, mx1fs2 and scb9328 boards
* Patches by Marc Leeman, 23 Jul 2004:
- Add define for the PCI/Memory Buffer Configuration Register
- corrected comments in cpu/mpc824x/cpu_init.c
* Add support for multiple serial interfaces
(for example to allow modem dial-in / dial-out)
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 6776dbf..904e7ea 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -40,6 +40,7 @@
#include <command.h>
#include <malloc.h>
#include <post.h>
+#include <serial.h>
#include <linux/types.h>
#include <linux/string.h> /* for strdup */
@@ -468,6 +469,13 @@
return (0);
}
+struct serial_device * default_serial_console (void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ return gd->do_mdm_init ? &serial_scc_device : &serial_smc_device;
+}
+
static void kbd_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mx1ads/mx1ads.c b/board/mx1ads/mx1ads.c
index 453e4bb..661fbab 100644
--- a/board/mx1ads/mx1ads.c
+++ b/board/mx1ads/mx1ads.c
@@ -23,9 +23,9 @@
* MA 02111-1307 USA
*/
-
#include <common.h>
-#include <mc9328.h>
+/*#include <mc9328.h>*/
+#include <asm/arch-arm920t/imx-regs.h>
/* ------------------------------------------------------------------------- */
@@ -67,7 +67,6 @@
* Miscellaneous platform dependent initialisations
*/
-
void SetAsynchMode(void) {
__asm__ (
"mrc p15,0,r0,c1,c0,0 \n"
@@ -85,42 +84,34 @@
volatile unsigned int tmp;
- mc9328sid = MX1_SIDR;
+ mc9328sid = SIDR;
- MX1_GPCR = 0x000003AB; /* I/O pad driving strength */
+ GPCR = 0x000003AB; /* I/O pad driving strength */
/* MX1_CS1U = 0x00000A00; */ /* SRAM initialization */
/* MX1_CS1L = 0x11110601; */
- MX1_MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
-
-/* MX1_MPCTL0 = 0x003f1437; */ /* setting for 192 MHz MCU PLL CLK */
+ MPCTL0 = 0x04632410; /* setting for 150 MHz MCU PLL CLK */
/* set FCLK divider 1 (i.e. FCLK to MCU PLL CLK) and
* BCLK divider to 2 (i.e. BCLK to 48 MHz)
*/
- MX1_CSCR = 0xAF000403;
+ CSCR = 0xAF000403;
- MX1_CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
- MX1_CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
+ CSCR |= 0x00200000; /* Trigger the restart bit(bit 21) */
+ CSCR &= 0xFFFF7FFF; /* Program PRESC bit(bit 15) to 0 to divide-by-1 */
/* setup cs4 for cs8900 ethernet */
- MX1_CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
- MX1_CS4L = 0x00001501;
+ CS4U = 0x00000F00; /* Initialize CS4 for CS8900 ethernet */
+ CS4L = 0x00001501;
- MX1_GIUS_A &= 0xFF3FFFFF;
- MX1_GPR_A &= 0xFF3FFFFF;
+ GIUS(0) &= 0xFF3FFFFF;
+ GPR(0) &= 0xFF3FFFFF;
tmp = *(unsigned int *)(0x1500000C);
tmp = *(unsigned int *)(0x1500000C);
-/* setup timer 1 as system timer */
-
- MX1_TPRER1 = 0x1f; /* divide by 32 */
- MX1_TCTL1 = 0x19; /* clock in from 32k Osc. */
-
-
SetAsynchMode();
gd->bd->bi_arch_number = 160; /* Arch number of MX1ADS Board */
@@ -131,19 +122,19 @@
dcache_enable();
/* set PERCLKs */
- MX1_PCDR = 0x00000055; /* set PERCLKS */
+ PCDR = 0x00000055; /* set PERCLKS */
/* PERCLK3 is only used by SSI so the SSI driver can set it any value it likes
* PERCLK1 and PERCLK2 are shared so DO NOT change it in any other place
* all sources selected as normal interrupt
*/
- MX1_INTTYPEH = 0;
- MX1_INTTYPEL = 0;
+/* MX1_INTTYPEH = 0;
+ MX1_INTTYPEL = 0;
+*/
return 0;
}
-
int board_late_init(void) {
setenv("stdout", "serial");
@@ -163,13 +154,10 @@
default :
printf ("MX1ADS board with UNKNOWN MC9328 cpu, Silicon ID 0x%08x \n",mc9328sid);
break;
-
}
-
return 0;
}
-
int dram_init (void) {
DECLARE_GLOBAL_DATA_PTR;
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index 09fc0f8..eb7fde5 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -24,7 +24,8 @@
*/
#include <common.h>
-#include <mc9328.h>
+/*#include <mc9328.h>*/
+#include <asm/arch/imx-regs.h>
typedef unsigned long * p_u32;
@@ -33,27 +34,26 @@
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/* Following Setting is for CSD1 */
-#define SFCTL 0x00221004
-#define reg_SFCTL __REG(SFCTL)
+#define SFCTL 0x00221004
+#define reg_SFCTL __REG(SFCTL)
-#define SYNCFLASH_A10 (0x00100000)
+#define SYNCFLASH_A10 (0x00100000)
-#define CMD_NORMAL (0x81020300) /* Normal Mode */
-#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
-#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
-#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
-#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
-#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
+#define CMD_NORMAL (0x81020300) /* Normal Mode */
+#define CMD_PREC (CMD_NORMAL + 0x10000000) /* Precharge Command */
+#define CMD_AUTO (CMD_NORMAL + 0x20000000) /* Auto Refresh Command */
+#define CMD_LMR (CMD_NORMAL + 0x30000000) /* Load Mode Register Command */
+#define CMD_LCR (CMD_NORMAL + 0x60000000) /* LCR Command */
+#define CMD_PROGRAM (CMD_NORMAL + 0x70000000)
-#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
+#define MODE_REG_VAL (CFG_FLASH_BASE+0x0008CC00) /* Cas Latency 3 */
/* LCR Command */
-#define LCR_READSTATUS (0x0001C000) /* 0x70 */
-#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
-#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
-#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
-#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
-
+#define LCR_READSTATUS (0x0001C000) /* 0x70 */
+#define LCR_ERASE_CONFIRM (0x00008000) /* 0x20 */
+#define LCR_ERASE_NVMODE (0x0000C000) /* 0x30 */
+#define LCR_PROG_NVMODE (0x00028000) /* 0xA0 */
+#define LCR_SR_CLEAR (0x00014000) /* 0x50 */
/* Get Status register */
u32 SF_SR(void) {
@@ -82,7 +82,6 @@
if ((tmp & 0x00000080) && (tmp & 0x0000001C)) {
printf ("SyncFlash Error code %08x\n",tmp);
-
};
if (tmp == 0x00800080) /* Test Bit 7 of SR */
@@ -98,7 +97,6 @@
reg_SFCTL = CMD_PREC; /* Set Precharge Command */
tmp = __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
-
}
/* set SyncFlash to normal mode */
@@ -128,7 +126,6 @@
while(!SF_Ready());
}
-
void SF_NvmodeErase(void) {
SF_PrechargeAll();
@@ -149,10 +146,8 @@
reg_SFCTL = CMD_NORMAL; /* Return to Normal mode */
__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0; /* Confirm not needed */
-
}
-
/****************************************************************************************/
ulong flash_init(void) {
@@ -195,7 +190,6 @@
return FLASH_BANK_SIZE;
}
-
void flash_print_info (flash_info_t *info) {
int i;
@@ -209,7 +203,6 @@
break;
}
-
switch (info->flash_id & FLASH_TYPEMASK) {
case (FLASH_MT28S4M16LC & FLASH_TYPEMASK):
printf("2x FLASH_MT28S4M16LC (16MB Total)\n");
@@ -236,7 +229,6 @@
printf ("\n");
}
-
/*-----------------------------------------------------------------------*/
int flash_erase (flash_info_t *info, int s_first, int s_last) {
diff --git a/board/mx1ads/u-boot.lds b/board/mx1ads/u-boot.lds
index 53743cd..649216a 100644
--- a/board/mx1ads/u-boot.lds
+++ b/board/mx1ads/u-boot.lds
@@ -23,7 +23,6 @@
* MA 02111-1307 USA
*/
-
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
@@ -34,7 +33,7 @@
. = ALIGN(4);
.text :
{
- cpu/mc9328/start.o (.text)
+ cpu/arm920t/start.o (.text)
*(.text)
}
diff --git a/board/mx1fs2/Makefile b/board/mx1fs2/Makefile
new file mode 100644
index 0000000..86aef5c
--- /dev/null
+++ b/board/mx1fs2/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := mx1fs2.o flash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/mx1fs2/config.mk b/board/mx1fs2/config.mk
new file mode 100644
index 0000000..59ab542
--- /dev/null
+++ b/board/mx1fs2/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of IMX sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0x08f00000
diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c
new file mode 100644
index 0000000..3a79a9e
--- /dev/null
+++ b/board/mx1fs2/flash.c
@@ -0,0 +1,914 @@
+/*
+ * (C) 2000-2004 Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ * (C) 2003 August Hoeraendl, Logotronic GmbH
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#undef CONFIG_FLASH_16BIT
+
+#include <common.h>
+
+#if defined CFG_JFFS_CUSTOM_PART
+#include <jffs2/jffs2.h>
+#endif
+
+#define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
+#define MAIN_SECT_SIZE MX1FS2_FLASH_SECT_SIZE
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+
+/*
+ * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
+ * has nothing to do with the flash chip being 8-bit or 16-bit.
+ */
+#ifdef CONFIG_FLASH_16BIT
+typedef unsigned short FLASH_PORT_WIDTH;
+typedef volatile unsigned short FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK 0xFFFF
+#else
+typedef unsigned long FLASH_PORT_WIDTH;
+typedef volatile unsigned long FLASH_PORT_WIDTHV;
+
+#define FLASH_ID_MASK 0xFFFFFFFF
+#endif
+
+#define FPW FLASH_PORT_WIDTH
+#define FPWV FLASH_PORT_WIDTHV
+
+#define ORMASK(size) ((-size) & OR_AM_MSK)
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+#if 0
+static ulong flash_get_size(FPWV * addr, flash_info_t * info);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+#endif
+static void flash_reset(flash_info_t * info);
+static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
+static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
+#define write_word(in, de, da) write_word_amd(in, de, da)
+#ifdef CFG_FLASH_PROTECTION
+static void flash_sync_real_protect(flash_info_t * info);
+#endif
+
+#if defined CFG_JFFS_CUSTOM_PART
+
+/**
+ * jffs2_part_info - get information about a JFFS2 partition
+ *
+ * @part_num: number of the partition you want to get info about
+ * @return: struct part_info* in case of success, 0 if failure
+ */
+
+static struct part_info part;
+static int current_part = -1;
+
+struct part_info *
+jffs2_part_info(int part_num)
+{
+ void *jffs2_priv_saved = part.jffs2_priv;
+
+ printf("jffs2_part_info: part_num=%i\n", part_num);
+
+ if (current_part == part_num)
+ return ∂
+
+ /* rootfs */
+ if (part_num == 0) {
+ memset(&part, 0, sizeof (part));
+
+ part.offset = (char *) MX1FS2_JFFS2_PART0_START;
+ part.size = MX1FS2_JFFS2_PART0_SIZE;
+
+ /* Mark the struct as ready */
+ current_part = part_num;
+
+ printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
+ printf("part.size = 0x%08x\n", (unsigned int) part.size);
+ }
+
+ /* userfs */
+ if (part_num == 1) {
+ memset(&part, 0, sizeof (part));
+
+ part.offset = (char *) MX1FS2_JFFS2_PART1_START;
+ part.size = MX1FS2_JFFS2_PART1_SIZE;
+
+ /* Mark the struct as ready */
+ current_part = part_num;
+
+ printf("part.offset = 0x%08x\n", (unsigned int) part.offset);
+ printf("part.size = 0x%08x\n", (unsigned int) part.size);
+ }
+
+ if (current_part == part_num) {
+ part.usr_priv = ¤t_part;
+ part.jffs2_priv = jffs2_priv_saved;
+ return ∂
+ }
+
+ printf("jffs2_part_info: end of partition table\n");
+ return 0;
+}
+#endif /* CFG_JFFS_CUSTOM_PART */
+
+/*-----------------------------------------------------------------------
+ * flash_init()
+ *
+ * sets up flash_info and returns size of FLASH (bytes)
+ */
+ulong
+flash_init(void)
+{
+ int i, j;
+ ulong size = 0;
+
+ for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+ ulong flashbase = 0;
+ flash_info[i].flash_id =
+ (FLASH_MAN_AMD & FLASH_VENDMASK) |
+ (FLASH_AM640U & FLASH_TYPEMASK);
+ flash_info[i].size = FLASH_BANK_SIZE;
+ flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+ memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+ switch (i) {
+ case 0:
+ flashbase = MX1FS2_FLASH_BASE;
+ break;
+ default:
+ panic("configured too many flash banks!\n");
+ break;
+ }
+ for (j = 0; j < flash_info[i].sector_count; j++) {
+ flash_info[i].start[j] = flashbase + j * MAIN_SECT_SIZE;
+ }
+ size += flash_info[i].size;
+ }
+
+ /* Protect monitor and environment sectors */
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + _bss_start - _armboot_start,
+ &flash_info[0]);
+
+ flash_protect(FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return size;
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void
+flash_reset(flash_info_t * info)
+{
+ FPWV *base = (FPWV *) (info->start[0]);
+
+ /* Put FLASH back in read mode */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL)
+ *base = (FPW) 0x00FF00FF; /* Intel Read Mode */
+ else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD)
+ *base = (FPW) 0x00F000F0; /* AMD Read Mode */
+}
+
+/*-----------------------------------------------------------------------
+ */
+#if 0
+static void
+flash_get_offsets(ulong base, flash_info_t * info)
+{
+ int i;
+
+ /* set up sector start address table */
+ if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL
+ && (info->flash_id & FLASH_BTYPE)) {
+ int bootsect_size; /* number of bytes/boot sector */
+ int sect_size; /* number of bytes/regular sector */
+
+ bootsect_size = 0x00002000 * (sizeof (FPW) / 2);
+ sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+ /* set sector offsets for bottom boot block type */
+ for (i = 0; i < 8; ++i) {
+ info->start[i] = base + (i * bootsect_size);
+ }
+ for (i = 8; i < info->sector_count; i++) {
+ info->start[i] = base + ((i - 7) * sect_size);
+ }
+ } else if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD
+ && (info->flash_id & FLASH_TYPEMASK) == FLASH_AM640U) {
+
+ int sect_size; /* number of bytes/sector */
+
+ sect_size = 0x00010000 * (sizeof (FPW) / 2);
+
+ /* set up sector start address table (uniform sector type) */
+ for (i = 0; i < info->sector_count; i++)
+ info->start[i] = base + (i * sect_size);
+ }
+}
+#endif /* 0 */
+
+/*-----------------------------------------------------------------------
+ */
+
+void
+flash_print_info(flash_info_t * info)
+{
+ int i;
+ uchar *boottype;
+ uchar *bootletter;
+ uchar *fmt;
+ uchar botbootletter[] = "B";
+ uchar topbootletter[] = "T";
+ uchar botboottype[] = "bottom boot sector";
+ uchar topboottype[] = "top boot sector";
+
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("missing or unknown FLASH type\n");
+ return;
+ }
+
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ printf("AMD ");
+ break;
+ case FLASH_MAN_BM:
+ printf("BRIGHT MICRO ");
+ break;
+ case FLASH_MAN_FUJ:
+ printf("FUJITSU ");
+ break;
+ case FLASH_MAN_SST:
+ printf("SST ");
+ break;
+ case FLASH_MAN_STM:
+ printf("STM ");
+ break;
+ case FLASH_MAN_INTEL:
+ printf("INTEL ");
+ break;
+ default:
+ printf("Unknown Vendor ");
+ break;
+ }
+
+ /* check for top or bottom boot, if it applies */
+ if (info->flash_id & FLASH_BTYPE) {
+ boottype = botboottype;
+ bootletter = botbootletter;
+ } else {
+ boottype = topboottype;
+ bootletter = topbootletter;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_AM640U:
+ fmt = "29LV641D (64 Mbit, uniform sectors)\n";
+ break;
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
+ fmt = "28F800C3%s (8 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL800B:
+ case FLASH_INTEL800T:
+ fmt = "28F800B3%s (8 Mbit, %s)\n";
+ break;
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ fmt = "28F160C3%s (16 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL160B:
+ case FLASH_INTEL160T:
+ fmt = "28F160B3%s (16 Mbit, %s)\n";
+ break;
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ fmt = "28F320C3%s (32 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL320B:
+ case FLASH_INTEL320T:
+ fmt = "28F320B3%s (32 Mbit, %s)\n";
+ break;
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ fmt = "28F640C3%s (64 Mbit, %s)\n";
+ break;
+ case FLASH_INTEL640B:
+ case FLASH_INTEL640T:
+ fmt = "28F640B3%s (64 Mbit, %s)\n";
+ break;
+ default:
+ fmt = "Unknown Chip Type\n";
+ break;
+ }
+
+ printf(fmt, bootletter, boottype);
+
+ printf(" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf(" Sector Start Addresses:");
+
+ for (i = 0; i < info->sector_count; ++i) {
+ if ((i % 5) == 0) {
+ printf("\n ");
+ }
+
+ printf(" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+
+ printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+#if 0
+ulong
+flash_get_size(FPWV * addr, flash_info_t * info)
+{
+ /* Write auto select command: read Manufacturer ID */
+
+ /* Write auto select command sequence and test FLASH answer */
+ addr[0x0555] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */
+ addr[0x02AA] = (FPW) 0x00550055; /* for AMD, Intel ignores this */
+ addr[0x0555] = (FPW) 0x00900090; /* selects Intel or AMD */
+
+ /* The manufacturer codes are only 1 byte, so just use 1 byte.
+ * This works for any bus width and any FLASH device width.
+ */
+ switch (addr[0] & 0xff) {
+
+ case (uchar) AMD_MANUFACT:
+ info->flash_id = FLASH_MAN_AMD;
+ break;
+
+ case (uchar) INTEL_MANUFACT:
+ info->flash_id = FLASH_MAN_INTEL;
+ break;
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ break;
+ }
+
+ /* Check 16 bits or 32 bits of ID so work on 32 or 16 bit bus. */
+ if (info->flash_id != FLASH_UNKNOWN)
+ switch (addr[1]) {
+
+ case (FPW) AMD_ID_LV640U: /* 29LV640 and 29LV641 have same ID */
+ info->flash_id += FLASH_AM640U;
+ info->sector_count = 128;
+ info->size = 0x00800000 * (sizeof (FPW) / 2);
+ break; /* => 8 or 16 MB */
+
+ case (FPW) INTEL_ID_28F800C3B:
+ info->flash_id += FLASH_28F800C3B;
+ info->sector_count = 23;
+ info->size = 0x00100000 * (sizeof (FPW) / 2);
+ break; /* => 1 or 2 MB */
+
+ case (FPW) INTEL_ID_28F800B3B:
+ info->flash_id += FLASH_INTEL800B;
+ info->sector_count = 23;
+ info->size = 0x00100000 * (sizeof (FPW) / 2);
+ break; /* => 1 or 2 MB */
+
+ case (FPW) INTEL_ID_28F160C3B:
+ info->flash_id += FLASH_28F160C3B;
+ info->sector_count = 39;
+ info->size = 0x00200000 * (sizeof (FPW) / 2);
+ break; /* => 2 or 4 MB */
+
+ case (FPW) INTEL_ID_28F160B3B:
+ info->flash_id += FLASH_INTEL160B;
+ info->sector_count = 39;
+ info->size = 0x00200000 * (sizeof (FPW) / 2);
+ break; /* => 2 or 4 MB */
+
+ case (FPW) INTEL_ID_28F320C3B:
+ info->flash_id += FLASH_28F320C3B;
+ info->sector_count = 71;
+ info->size = 0x00400000 * (sizeof (FPW) / 2);
+ break; /* => 4 or 8 MB */
+
+ case (FPW) INTEL_ID_28F320B3B:
+ info->flash_id += FLASH_INTEL320B;
+ info->sector_count = 71;
+ info->size = 0x00400000 * (sizeof (FPW) / 2);
+ break; /* => 4 or 8 MB */
+
+ case (FPW) INTEL_ID_28F640C3B:
+ info->flash_id += FLASH_28F640C3B;
+ info->sector_count = 135;
+ info->size = 0x00800000 * (sizeof (FPW) / 2);
+ break; /* => 8 or 16 MB */
+
+ case (FPW) INTEL_ID_28F640B3B:
+ info->flash_id += FLASH_INTEL640B;
+ info->sector_count = 135;
+ info->size = 0x00800000 * (sizeof (FPW) / 2);
+ break; /* => 8 or 16 MB */
+
+ default:
+ info->flash_id = FLASH_UNKNOWN;
+ info->sector_count = 0;
+ info->size = 0;
+ return (0); /* => no or unknown flash */
+ }
+
+ flash_get_offsets((ulong) addr, info);
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+
+ return (info->size);
+}
+#endif /* 0 */
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+
+static void
+flash_sync_real_protect(flash_info_t * info)
+{
+ FPWV *addr = (FPWV *) (info->start[0]);
+ FPWV *sect;
+ int i;
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ /* check for protected sectors */
+ *addr = (FPW) 0x00900090;
+ for (i = 0; i < info->sector_count; i++) {
+ /* read sector protection at sector address, (A7 .. A0) = 0x02.
+ * D0 = 1 for each device if protected.
+ * If at least one device is protected the sector is marked
+ * protected, but mixed protected and unprotected devices
+ * within a sector should never happen.
+ */
+ sect = (FPWV *) (info->start[i]);
+ info->protect[i] =
+ (sect[2] & (FPW) (0x00010001)) ? 1 : 0;
+ }
+
+ /* Put FLASH back in read mode */
+ flash_reset(info);
+ break;
+
+ case FLASH_AM640U:
+ default:
+ /* no hardware protect that we support */
+ break;
+ }
+}
+#endif
+
+/*-----------------------------------------------------------------------
+ */
+
+int
+flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+ FPWV *addr;
+ int flag, prot, sect;
+ int intel = (info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL;
+ ulong start, now, last;
+ int rcode = 0;
+
+ if ((s_first < 0) || (s_first > s_last)) {
+ if (info->flash_id == FLASH_UNKNOWN) {
+ printf("- missing\n");
+ } else {
+ printf("- no sectors to erase\n");
+ }
+ return 1;
+ }
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_INTEL800B:
+ case FLASH_INTEL160B:
+ case FLASH_INTEL320B:
+ case FLASH_INTEL640B:
+ case FLASH_28F800C3B:
+ case FLASH_28F160C3B:
+ case FLASH_28F320C3B:
+ case FLASH_28F640C3B:
+ case FLASH_AM640U:
+ break;
+ case FLASH_UNKNOWN:
+ default:
+ printf("Can't erase unknown flash type %08lx - aborted\n",
+ info->flash_id);
+ return 1;
+ }
+
+ prot = 0;
+ for (sect = s_first; sect <= s_last; ++sect) {
+ if (info->protect[sect]) {
+ prot++;
+ }
+ }
+
+ if (prot) {
+ printf("- Warning: %d protected sectors will not be erased!\n",
+ prot);
+ } else {
+ printf("\n");
+ }
+
+ start = get_timer(0);
+ last = start;
+
+ /* Start erase on unprotected sectors */
+ for (sect = s_first; sect <= s_last && rcode == 0; sect++) {
+
+ if (info->protect[sect] != 0) /* protected, skip it */
+ continue;
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ addr = (FPWV *) (info->start[sect]);
+ if (intel) {
+ *addr = (FPW) 0x00500050; /* clear status register */
+ *addr = (FPW) 0x00200020; /* erase setup */
+ *addr = (FPW) 0x00D000D0; /* erase confirm */
+ } else {
+ /* must be AMD style if not Intel */
+ FPWV *base; /* first address in bank */
+
+ base = (FPWV *) (info->start[0]);
+ base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
+ base[0x02AA] = (FPW) 0x00550055; /* unlock */
+ base[0x0555] = (FPW) 0x00800080; /* erase mode */
+ base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
+ base[0x02AA] = (FPW) 0x00550055; /* unlock */
+ *addr = (FPW) 0x00300030; /* erase sector */
+ }
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ /* wait at least 50us for AMD, 80us for Intel.
+ * Let's wait 1 ms.
+ */
+ udelay(1000);
+
+ while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) {
+ printf("Timeout\n");
+
+ if (intel) {
+ /* suspend erase */
+ *addr = (FPW) 0x00B000B0;
+ }
+
+ flash_reset(info); /* reset to read mode */
+ rcode = 1; /* failed */
+ break;
+ }
+
+ /* show that we're waiting */
+ if ((now - last) > 1000) { /* every second */
+ putc('.');
+ last = now;
+ }
+ }
+
+ flash_reset(info); /* reset to read mode */
+ }
+
+ printf(" done\n");
+ return rcode;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+int
+bad_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ FPW data = 0; /* 16 or 32 bit word, matches flash bus width on MPC8XX */
+ int bytes; /* number of bytes to program in current word */
+ int left; /* number of bytes left to program */
+ int i, res;
+
+ for (left = cnt, res = 0;
+ left > 0 && res == 0;
+ addr += sizeof (data), left -= sizeof (data) - bytes) {
+
+ bytes = addr & (sizeof (data) - 1);
+ addr &= ~(sizeof (data) - 1);
+
+ /* combine source and destination data so can program
+ * an entire word of 16 or 32 bits
+ */
+ for (i = 0; i < sizeof (data); i++) {
+ data <<= 8;
+ if (i < bytes || i - bytes >= left)
+ data += *((uchar *) addr + i);
+ else
+ data += *src++;
+ }
+
+ /* write one word to the flash */
+ switch (info->flash_id & FLASH_VENDMASK) {
+ case FLASH_MAN_AMD:
+ res = write_word_amd(info, (FPWV *) addr, data);
+ break;
+ case FLASH_MAN_INTEL:
+ res = write_word_intel(info, (FPWV *) addr, data);
+ break;
+ default:
+ /* unknown flash type, error! */
+ printf("missing or unknown FLASH type\n");
+ res = 1; /* not really a timeout, but gives error */
+ break;
+ }
+ }
+
+ return (res);
+}
+
+/**
+ * write_buf: - Copy memory to flash.
+ *
+ * @param info:
+ * @param src: source of copy transaction
+ * @param addr: where to copy to
+ * @param cnt: number of bytes to copy
+ *
+ * @return error code
+ */
+
+int
+write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong cp, wp;
+ FPW data;
+ int l;
+ int i, rc;
+
+ wp = (addr & ~1); /* get lower word aligned address */
+
+ /* handle unaligned start bytes */
+ if ((l = addr - wp) != 0) {
+ data = 0;
+ for (i = 0, cp = wp; i < l; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+ for (; i < 2 && cnt > 0; ++i) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ ++cp;
+ }
+ for (; cnt == 0 && i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+ return (rc);
+ }
+ wp += 2;
+ }
+
+ /* handle word aligned part */
+ while (cnt >= 2) {
+ /* data = *((vushort*)src); */
+ data = *((FPW *) src);
+ if ((rc = write_word(info, (FPWV *)wp, data)) != 0) {
+ return (rc);
+ }
+ src += sizeof (FPW);
+ wp += sizeof (FPW);
+ cnt -= sizeof (FPW);
+ }
+
+ if (cnt == 0)
+ return ERR_OK;
+
+ /*
+ * handle unaligned tail bytes
+ */
+ data = 0;
+ for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) {
+ data = (data >> 8) | (*src++ << 8);
+ --cnt;
+ }
+ for (; i < 2; ++i, ++cp) {
+ data = (data >> 8) | (*(uchar *) cp << 8);
+ }
+
+ return write_word(info, (FPWV *)wp, data);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for AMD FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_amd(flash_info_t * info, FPWV * dest, FPW data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+ FPWV *base; /* first address in flash bank */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ base = (FPWV *) (info->start[0]);
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ base[0x0555] = (FPW) 0x00AA00AA; /* unlock */
+ base[0x02AA] = (FPW) 0x00550055; /* unlock */
+ base[0x0555] = (FPW) 0x00A000A0; /* selects program mode */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ /* data polling for D7 */
+ while (res == 0
+ && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
+ if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) {
+ *dest = (FPW) 0x00F000F0; /* reset bank */
+ printf("SHA timeout\n");
+ res = 1;
+ }
+ }
+
+ return (res);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash for Intel FLASH
+ * A word is 16 or 32 bits, whichever the bus width of the flash bank
+ * (not an individual chip) is.
+ *
+ * returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int
+write_word_intel(flash_info_t * info, FPWV * dest, FPW data)
+{
+ ulong start;
+ int flag;
+ int res = 0; /* result, assume success */
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*dest & data) != data) {
+ return (2);
+ }
+
+ /* Disable interrupts which might cause a timeout here */
+ flag = disable_interrupts();
+
+ *dest = (FPW) 0x00500050; /* clear status register */
+ *dest = (FPW) 0x00FF00FF; /* make sure in read mode */
+ *dest = (FPW) 0x00400040; /* program setup */
+
+ *dest = data; /* start programming the data */
+
+ /* re-enable interrupts if necessary */
+ if (flag)
+ enable_interrupts();
+
+ start = get_timer(0);
+
+ while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
+ if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+ *dest = (FPW) 0x00B000B0; /* Suspend program */
+ res = 1;
+ }
+ }
+
+ if (res == 0 && (*dest & (FPW) 0x00100010))
+ res = 1; /* write failed, time out error is close enough */
+
+ *dest = (FPW) 0x00500050; /* clear status register */
+ *dest = (FPW) 0x00FF00FF; /* make sure in read mode */
+
+ return (res);
+}
+
+#ifdef CFG_FLASH_PROTECTION
+/*-----------------------------------------------------------------------
+ */
+int
+flash_real_protect(flash_info_t * info, long sector, int prot)
+{
+ int rcode = 0; /* assume success */
+ FPWV *addr; /* address of sector */
+ FPW value;
+
+ addr = (FPWV *) (info->start[sector]);
+
+ switch (info->flash_id & FLASH_TYPEMASK) {
+ case FLASH_28F800C3B:
+ case FLASH_28F800C3T:
+ case FLASH_28F160C3B:
+ case FLASH_28F160C3T:
+ case FLASH_28F320C3B:
+ case FLASH_28F320C3T:
+ case FLASH_28F640C3B:
+ case FLASH_28F640C3T:
+ flash_reset(info); /* make sure in read mode */
+ *addr = (FPW) 0x00600060L; /* lock command setup */
+ if (prot)
+ *addr = (FPW) 0x00010001L; /* lock sector */
+ else
+ *addr = (FPW) 0x00D000D0L; /* unlock sector */
+ flash_reset(info); /* reset to read mode */
+
+ /* now see if it really is locked/unlocked as requested */
+ *addr = (FPW) 0x00900090;
+ /* read sector protection at sector address, (A7 .. A0) = 0x02.
+ * D0 = 1 for each device if protected.
+ * If at least one device is protected the sector is marked
+ * protected, but return failure. Mixed protected and
+ * unprotected devices within a sector should never happen.
+ */
+ value = addr[2] & (FPW) 0x00010001;
+ if (value == 0)
+ info->protect[sector] = 0;
+ else if (value == (FPW) 0x00010001)
+ info->protect[sector] = 1;
+ else {
+ /* error, mixed protected and unprotected */
+ rcode = 1;
+ info->protect[sector] = 1;
+ }
+ if (info->protect[sector] != prot)
+ rcode = 1; /* failed to protect/unprotect as requested */
+
+ /* reload all protection bits from hardware for now */
+ flash_sync_real_protect(info);
+ break;
+
+ case FLASH_AM640U:
+ default:
+ /* no hardware protect that we support */
+ info->protect[sector] = prot;
+ break;
+ }
+
+ return rcode;
+}
+#endif
diff --git a/board/mx1fs2/intel.h b/board/mx1fs2/intel.h
new file mode 100644
index 0000000..8db5dd4
--- /dev/null
+++ b/board/mx1fs2/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef FLASH_INTEL_H
+#define FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define CFI_CHIP_INTEL_28F320J3A 0x0016
+#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
+#define CFI_CHIP_INTEL_28F640J3A 0x0017
+#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
+#define CFI_CHIP_INTEL_28F128J3A 0x0018
+#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define CFI_CHIP_INTEL_28F640K3 0x8801
+#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
+#define CFI_CHIP_INTEL_28F128K3 0x8802
+#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
+#define CFI_CHIP_INTEL_28F256K3 0x8803
+#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
+#define CFI_CHIP_INTEL_28F640K18 0x8805
+#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
+#define CFI_CHIP_INTEL_28F128K18 0x8806
+#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
+#define CFI_CHIP_INTEL_28F256K18 0x8807
+#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/board/mx1fs2/memsetup.S b/board/mx1fs2/memsetup.S
new file mode 100644
index 0000000..5ec751b
--- /dev/null
+++ b/board/mx1fs2/memsetup.S
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl memsetup
+memsetup:
+
+ mov r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+ ldr r0, =PCDR
+ ldr r1, =CFG_PCDR_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 0 */
+
+ ldr r0, =MPCTL0
+ ldr r1, =CFG_MPCTL0_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 1 */
+
+ ldr r0, =MPCTL1
+ ldr r1, =CFG_MPCTL1_VAL
+ str r1, [r0]
+
+/* set mpll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<21)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+/* set System PLL Control Register 0 */
+
+ ldr r0, =SPCTL0
+ ldr r1, =CFG_SPCTL0_VAL
+ str r1, [r0]
+
+/* set System PLL Control Register 1 */
+
+ ldr r0, =SPCTL1
+ ldr r1, =CFG_SPCTL1_VAL
+ str r1, [r0]
+
+/* set spll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<22)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+ ldr r0, =CSCR
+ ldr r1, =CFG_CSCR_VAL
+ str r1, [r0]
+
+ ldr r0, =GPCR
+ ldr r1, =CFG_GPCR_VAL
+ str r1, [r0]
+
+/*
+ * I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ * this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+ *
+ * Slapping this into my bootloader does the trick...
+ *
+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
+ * register
+ *
+ */
+ MRC p15,0,r0,c1,c0,0
+/* ORR r0,r0,#0xC0000000 async mode */
+/* ORR r0,r0,#0x40000000 sync mode */
+ ORR r0,r0,#0xC0000000
+ MCR p15,0,r0,c1,c0,0
+
+ ldr r0, =GIUS(0)
+ ldr r1, =CFG_GIUS_A_VAL
+ str r1, [r0]
+
+ ldr r0, =FMCR
+ ldr r1, =CFG_FMCR_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0U
+ ldr r1, =CFG_CS0U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0L
+ ldr r1, =CFG_CS0L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1U
+ ldr r1, =CFG_CS1U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1L
+ ldr r1, =CFG_CS1L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4U
+ ldr r1, =CFG_CS4U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4L
+ ldr r1, =CFG_CS4L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5U
+ ldr r1, =CFG_CS5U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5L
+ ldr r1, =CFG_CS5L_VAL
+ str r1, [r0]
+
+/* SDRAM Setup */
+
+ ldr r1,=0x00221000 /* adr of SDCTRL0 */
+ ldr r0,=0x92120200
+ str r0,[r1,#0] /* put in precharge command mode */
+ ldr r2,=0x08200000 /* adr for precharge cmd */
+ ldr r0,[r2,#0] /* precharge */
+ ldr r0,=0xA2120200
+ ldr r2,=0x08000000 /* start of SDRAM */
+ str r0,[r1,#0] /* put in auto-refresh mode */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,[r2,#0] /* auto-refresh */
+ ldr r0,=0xB2120200
+ ldr r2,=0x08111800
+ str r0,[r1,#0] /* setup for mode register of SDRAM */
+ ldr r0,[r2,#0] /* program mode register */
+ ldr r0,=0x82124267
+ str r0,[r1,#0] /* back to normal operation */
+
+ mov pc,r10
diff --git a/board/mx1fs2/mx1fs2.c b/board/mx1fs2/mx1fs2.c
new file mode 100644
index 0000000..f51085a
--- /dev/null
+++ b/board/mx1fs2/mx1fs2.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#include <asm/arch/imx-regs.h>
+
+#define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+
+extern void imx_gpio_mode(int gpio_mode);
+
+static void logo_init(void)
+{
+ imx_gpio_mode(PD15_PF_LD0);
+ imx_gpio_mode(PD16_PF_LD1);
+ imx_gpio_mode(PD17_PF_LD2);
+ imx_gpio_mode(PD18_PF_LD3);
+ imx_gpio_mode(PD19_PF_LD4);
+ imx_gpio_mode(PD20_PF_LD5);
+ imx_gpio_mode(PD21_PF_LD6);
+ imx_gpio_mode(PD22_PF_LD7);
+ imx_gpio_mode(PD23_PF_LD8);
+ imx_gpio_mode(PD24_PF_LD9);
+ imx_gpio_mode(PD25_PF_LD10);
+ imx_gpio_mode(PD26_PF_LD11);
+ imx_gpio_mode(PD27_PF_LD12);
+ imx_gpio_mode(PD28_PF_LD13);
+ imx_gpio_mode(PD29_PF_LD14);
+ imx_gpio_mode(PD30_PF_LD15);
+ imx_gpio_mode(PD14_PF_FLM_VSYNC);
+ imx_gpio_mode(PD13_PF_LP_HSYNC);
+ imx_gpio_mode(PD6_PF_LSCLK);
+ imx_gpio_mode(GPIO_PORTD | GPIO_OUT | GPIO_GPIO);
+ imx_gpio_mode(PD11_PF_CONTRAST);
+ imx_gpio_mode(PD10_PF_SPL_SPR);
+
+ LCDC_RMCR = 0x00000000;
+ LCDC_PCR = PCR_COLOR | PCR_PBSIZ_8 | PCR_BPIX_16 | PCR_PCD(5);
+ LCDC_HCR = HCR_H_WIDTH(2);
+ LCDC_VCR = VCR_V_WIDTH(2);
+
+ LCDC_PWMR = 0x00000380; /* contrast to 0x80 middle (is best !!!) */
+ LCDC_SSA = 0x10040000; /* image in flash */
+
+ LCDC_SIZE = SIZE_XMAX(320) | SIZE_YMAX(240); /* screen size */
+
+ LCDC_VPW = 0x000000A0; /* Virtual Page Width Register */
+ LCDC_POS = 0x00000000; /* panning offset 0 (0 pixel offset) */
+
+ /* disable Cursor */
+ LCDC_CPOS = 0x00000000;
+
+ /* fixed burst length */
+ LCDC_DMACR = DMACR_BURST | DMACR_HM(8) | DMACR_TM(2);
+
+ /* enable LCD */
+ DR(3) |= 0x00001000;
+ LCDC_RMCR = RMCR_LCDC_EN;
+
+}
+
+int
+board_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_arch_number = 470;
+ gd->bd->bi_boot_params = 0x08000100;
+serial_init();
+ logo_init();
+ return 0;
+}
+
+int
+dram_init(void)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+ gd->bd->bi_dram[0].start = MX1FS2_SDRAM_1;
+ gd->bd->bi_dram[0].size = MX1FS2_SDRAM_1_SIZE;
+#endif
+ return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ */
+
+void
+show_boot_progress(int status)
+{
+ /* We use this as a hook to disable serial ports just before booting
+ * This way we suppress the "uncompressing linux..." message
+ */
+#ifdef CONFIG_SILENT_CONSOLE
+ if( status == 8) {
+ if( getenv("silent") != NULL ) {
+ *(volatile unsigned long *)0x206080 &= ~1;
+ *(volatile unsigned long *)0x207080 &= ~1;
+ }
+ }
+#endif
+ return;
+}
diff --git a/board/mx1fs2/u-boot.lds b/board/mx1fs2/u-boot.lds
new file mode 100644
index 0000000..5076303
--- /dev/null
+++ b/board/mx1fs2/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c
index dd59969..408ada0 100644
--- a/board/netphone/phone_console.c
+++ b/board/netphone/phone_console.c
@@ -326,7 +326,6 @@
int drv_phone_init(void)
{
device_t console_dev;
- char *penv;
console_init();
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index a784e34..1aed61b 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -256,11 +256,13 @@
long dram_size = 0;
extern long spd_sdram (void);
volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if 0
#if !defined(CONFIG_RAM_AS_FLASH)
volatile ccsr_lbc_t *lbc= &immap->im_lbc;
sys_info_t sysinfo;
uint temp_lbcdll = 0;
#endif
+#endif /* 0 */
#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
volatile ccsr_gur_t *gur= &immap->im_gur;
#endif
@@ -279,7 +281,7 @@
dram_size = fixed_sdram ();
#endif
-#if XXX
+#if 0
#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
get_sys_info(&sysinfo);
/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
diff --git a/board/scb9328/Makefile b/board/scb9328/Makefile
new file mode 100644
index 0000000..212efcc
--- /dev/null
+++ b/board/scb9328/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2000-2004
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = lib$(BOARD).a
+
+OBJS := scb9328.o flash.o
+SOBJS := memsetup.o
+
+$(LIB): $(OBJS) $(SOBJS)
+ $(AR) crv $@ $^
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+ $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff --git a/board/scb9328/config.mk b/board/scb9328/config.mk
new file mode 100644
index 0000000..8d1d79a
--- /dev/null
+++ b/board/scb9328/config.mk
@@ -0,0 +1,10 @@
+#
+# This config file is used for compilation of scb93328 sources
+#
+# You might change location of U-Boot in memory by setting right TEXT_BASE.
+# This allows for example having one copy located at the end of ram and stored
+# in flash device and later on while developing use other location to test
+# the code in RAM device only.
+#
+
+TEXT_BASE = 0x08f00000
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
new file mode 100644
index 0000000..1b56f8c
--- /dev/null
+++ b/board/scb9328/flash.c
@@ -0,0 +1,321 @@
+/*
+ * Copyright (C) 2003 ETC s.r.o.
+ *
+ * This code was inspired by Marius Groeger and Kyle Harris code
+ * available in other board ports for U-Boot
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Written by Peter Figuli <peposh@etc.sk>, 2003.
+ *
+ */
+
+#include <common.h>
+#include "intel.h"
+
+
+/*
+ * This code should handle CFI FLASH memory device. This code is very
+ * minimalistic approach without many essential error handling code as well.
+ * Because U-Boot actually is missing smart handling of FLASH device,
+ * we just set flash_id to anything else to FLASH_UNKNOW, so common code
+ * can call us without any restrictions.
+ * TODO: Add CFI Query, to be able to determine FLASH device.
+ * TODO: Add error handling code
+ * NOTE: This code was tested with BUS_WIDTH 4 and ITERLEAVE 2 only, but
+ * hopefully may work with other configurations.
+ */
+
+#if ( SCB9328_FLASH_BUS_WIDTH == 1 )
+# define FLASH_BUS vu_char
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# else
+# error "With 8bit bus only one chip is allowed"
+# endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 2 )
+# define FLASH_BUS vu_short
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+# define FLASH_CMD( x ) (( x << 8 )| x )
+# else
+# error "With 16bit bus only 1 or 2 chip(s) are allowed"
+# endif
+
+
+#elif ( SCB9328_FLASH_BUS_WIDTH == 4 )
+# define FLASH_BUS vu_long
+# if ( SCB9328_FLASH_INTERLEAVE == 1 )
+# define FLASH_CMD( x ) x
+# elif ( SCB9328_FLASH_INTERLEAVE == 2 )
+# define FLASH_CMD( x ) (( x << 16 )| x )
+# elif ( SCB9328_FLASH_INTERLEAVE == 4 )
+# define FLASH_CMD( x ) (( x << 24 )|( x << 16 ) ( x << 8 )| x )
+# else
+# error "With 32bit bus only 1,2 or 4 chip(s) are allowed"
+# endif
+
+#else
+# error "Flash bus width might be 1,2,4 for 8,16,32 bit configuration"
+#endif
+
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+
+static FLASH_BUS flash_status_reg (void)
+{
+
+ FLASH_BUS *addr = (FLASH_BUS *) 0;
+
+ *addr = FLASH_CMD (CFI_INTEL_CMD_READ_STATUS_REGISTER);
+
+ return *addr;
+}
+
+static int flash_ready (ulong timeout)
+{
+ int ok = 1;
+
+ reset_timer_masked ();
+ while ((flash_status_reg () & FLASH_CMD (CFI_INTEL_SR_READY)) !=
+ FLASH_CMD (CFI_INTEL_SR_READY)) {
+ if (get_timer_masked () > timeout && timeout != 0) {
+ ok = 0;
+ break;
+ }
+ }
+ return ok;
+}
+
+#if ( CFG_MAX_FLASH_BANKS != 1 )
+# error "SCB9328 platform has only one flash bank!"
+#endif
+
+
+ulong flash_init (void)
+{
+ int i;
+ unsigned long address = SCB9328_FLASH_BASE;
+
+ flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
+ flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+ flash_info[0].flash_id = INTEL_MANUFACT;
+ memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+
+ for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+ flash_info[0].start[i] = address;
+#ifdef SCB9328_FLASH_UNLOCK
+ /* Some devices are hw locked after start. */
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_LOCK_SETUP);
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_UNLOCK_BLOCK);
+ flash_ready (0);
+ *((FLASH_BUS *) address) = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+#endif
+ address += SCB9328_FLASH_SECT_SIZE;
+ }
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_FLASH_BASE,
+ CFG_FLASH_BASE + monitor_flash_len - 1,
+ &flash_info[0]);
+
+ flash_protect (FLAG_PROTECT_SET,
+ CFG_ENV_ADDR,
+ CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[0]);
+
+ return SCB9328_FLASH_BANK_SIZE;
+}
+
+void flash_print_info (flash_info_t * info)
+{
+ int i;
+
+ printf (" Intel vendor\n");
+ printf (" Size: %ld MB in %d Sectors\n",
+ info->size >> 20, info->sector_count);
+
+ printf (" Sector Start Addresses:");
+ for (i = 0; i < info->sector_count; i++) {
+ if (!(i % 5)) {
+ printf ("\n");
+ }
+
+ printf (" %08lX%s", info->start[i],
+ info->protect[i] ? " (RO)" : " ");
+ }
+ printf ("\n");
+}
+
+
+int flash_erase (flash_info_t * info, int s_first, int s_last)
+{
+ int flag, non_protected = 0, sector;
+ int rc = ERR_OK;
+
+ FLASH_BUS *address;
+
+ for (sector = s_first; sector <= s_last; sector++) {
+ if (!info->protect[sector]) {
+ non_protected++;
+ }
+ }
+
+ if (!non_protected) {
+ return ERR_PROTECTED;
+ }
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+ flag = disable_interrupts ();
+
+
+ /* Start erase on unprotected sectors */
+ for (sector = s_first; sector <= s_last && !ctrlc (); sector++) {
+ if (info->protect[sector]) {
+ printf ("Protected sector %2d skipping...\n", sector);
+ continue;
+ } else {
+ printf ("Erasing sector %2d ... ", sector);
+ }
+
+ address = (FLASH_BUS *) (info->start[sector]);
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
+ *address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
+ if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+ *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+ printf ("ok.\n");
+ } else {
+ *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+ rc = ERR_TIMOUT;
+ printf ("timeout! Aborting...\n");
+ break;
+ }
+ *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+ }
+ if (ctrlc ())
+ printf ("User Interrupt!\n");
+
+ /* allow flash to settle - wait 10 ms */
+ udelay_masked (10000);
+ if (flag) {
+ enable_interrupts ();
+ }
+
+ return rc;
+}
+
+static int write_data (flash_info_t * info, ulong dest, FLASH_BUS data)
+{
+ FLASH_BUS *address = (FLASH_BUS *) dest;
+ int rc = ERR_OK;
+ int flag;
+
+ /* Check if Flash is (sufficiently) erased */
+ if ((*address & data) != data) {
+ return ERR_NOT_ERASED;
+ }
+
+ /*
+ * Disable interrupts which might cause a timeout
+ * here. Remember that our exception vectors are
+ * at address 0 in the flash, and we don't want a
+ * (ticker) exception to happen while the flash
+ * chip is in programming mode.
+ */
+
+ flag = disable_interrupts ();
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
+ *address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
+ *address = data;
+
+ if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+ *address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
+ rc = ERR_TIMOUT;
+ printf ("timeout! Aborting...\n");
+ }
+
+ *address = FLASH_CMD (CFI_INTEL_CMD_READ_ARRAY);
+ if (flag) {
+ enable_interrupts ();
+ }
+
+ return rc;
+}
+
+int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+ ulong read_addr, write_addr;
+ FLASH_BUS data;
+ int i, result = ERR_OK;
+
+
+ read_addr = addr & ~(sizeof (FLASH_BUS) - 1);
+ write_addr = read_addr;
+ if (read_addr != addr) {
+ data = 0;
+ for (i = 0; i < sizeof (FLASH_BUS); i++) {
+ if (read_addr < addr || cnt == 0) {
+ data |= *((uchar *) read_addr) << i * 8;
+ } else {
+ data |= (*src++) << i * 8;
+ cnt--;
+ }
+ read_addr++;
+ }
+ if ((result = write_data (info, write_addr, data)) != ERR_OK) {
+ return result;
+ }
+ write_addr += sizeof (FLASH_BUS);
+ }
+ for (; cnt >= sizeof (FLASH_BUS); cnt -= sizeof (FLASH_BUS)) {
+ if ((result = write_data (info, write_addr,
+ *((FLASH_BUS *) src))) != ERR_OK) {
+ return result;
+ }
+ write_addr += sizeof (FLASH_BUS);
+ src += sizeof (FLASH_BUS);
+ }
+ if (cnt > 0) {
+ read_addr = write_addr;
+ data = 0;
+ for (i = 0; i < sizeof (FLASH_BUS); i++) {
+ if (cnt > 0) {
+ data |= (*src++) << i * 8;
+ cnt--;
+ } else {
+ data |= *((uchar *) read_addr) << i * 8;
+ }
+ read_addr++;
+ }
+ if ((result = write_data (info, write_addr, data)) != 0) {
+ return result;
+ }
+ }
+ return ERR_OK;
+}
diff --git a/board/scb9328/intel.h b/board/scb9328/intel.h
new file mode 100644
index 0000000..77498b6
--- /dev/null
+++ b/board/scb9328/intel.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (C) 2002 ETC s.r.o.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the ETC s.r.o. nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Written by Marcel Telka <marcel@telka.sk>, 2002.
+ *
+ * Documentation:
+ * [1] Intel Corporation, "3 Volt Intel Strata Flash Memory 28F128J3A, 28F640J3A,
+ * 28F320J3A (x8/x16)", April 2002, Order Number: 290667-011
+ * [2] Intel Corporation, "3 Volt Synchronous Intel Strata Flash Memory 28F640K3, 28F640K18,
+ * 28F128K3, 28F128K18, 28F256K3, 28F256K18 (x16)", June 2002, Order Number: 290737-005
+ *
+ * This file is taken from OpenWinCE project hosted by SourceForge.net
+ *
+ */
+
+#ifndef FLASH_INTEL_H
+#define FLASH_INTEL_H
+
+#include <common.h>
+
+/* Intel CFI commands - see Table 4. in [1] and Table 3. in [2] */
+
+#define CFI_INTEL_CMD_READ_ARRAY 0xFF /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_IDENTIFIER 0x90 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_QUERY 0x98 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_READ_STATUS_REGISTER 0x70 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CLEAR_STATUS_REGISTER 0x50 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM1 0x40 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_PROGRAM2 0x10 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_WRITE_TO_BUFFER 0xE8 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_CONFIRM 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_BLOCK_ERASE 0x20 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_SUSPEND 0xB0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_RESUME 0xD0 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_SETUP 0x60 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_BLOCK 0x01 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_UNLOCK_BLOCK 0xD0 /* 28FxxxJ3A - unlocks all blocks, 28FFxxxK3, 28FxxxK18 */
+#define CFI_INTEL_CMD_LOCK_DOWN_BLOCK 0x2F /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel CFI Status Register bits - see Table 6. in [1] and Table 7. in [2] */
+
+#define CFI_INTEL_SR_READY 1 << 7 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_SUSPEND 1 << 6 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_ERASE_ERROR 1 << 5 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_ERROR 1 << 4 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_VPEN_ERROR 1 << 3 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_PROGRAM_SUSPEND 1 << 2 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BLOCK_LOCKED 1 << 1 /* 28FxxxJ3A, 28FxxxK3, 28FxxxK18 */
+#define CFI_INTEL_SR_BEFP 1 << 0 /* 28FxxxK3, 28FxxxK18 */
+
+/* Intel flash device ID codes for 28FxxxJ3A - see Table 5. in [1] */
+
+#define CFI_CHIP_INTEL_28F320J3A 0x0016
+#define CFI_CHIPN_INTEL_28F320J3A "28F320J3A"
+#define CFI_CHIP_INTEL_28F640J3A 0x0017
+#define CFI_CHIPN_INTEL_28F640J3A "28F640J3A"
+#define CFI_CHIP_INTEL_28F128J3A 0x0018
+#define CFI_CHIPN_INTEL_28F128J3A "28F128J3A"
+
+/* Intel flash device ID codes for 28FxxxK3 and 28FxxxK18 - see Table 8. in [2] */
+
+#define CFI_CHIP_INTEL_28F640K3 0x8801
+#define CFI_CHIPN_INTEL_28F640K3 "28F640K3"
+#define CFI_CHIP_INTEL_28F128K3 0x8802
+#define CFI_CHIPN_INTEL_28F128K3 "28F128K3"
+#define CFI_CHIP_INTEL_28F256K3 0x8803
+#define CFI_CHIPN_INTEL_28F256K3 "28F256K3"
+#define CFI_CHIP_INTEL_28F640K18 0x8805
+#define CFI_CHIPN_INTEL_28F640K18 "28F640K18"
+#define CFI_CHIP_INTEL_28F128K18 0x8806
+#define CFI_CHIPN_INTEL_28F128K18 "28F128K18"
+#define CFI_CHIP_INTEL_28F256K18 0x8807
+#define CFI_CHIPN_INTEL_28F256K18 "28F256K18"
+
+#endif /* FLASH_INTEL_H */
diff --git a/board/scb9328/memsetup.S b/board/scb9328/memsetup.S
new file mode 100644
index 0000000..be5650a
--- /dev/null
+++ b/board/scb9328/memsetup.S
@@ -0,0 +1,203 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
+ * 02111-1307, USA.
+ *
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx-regs.h>
+
+.globl memsetup
+memsetup:
+
+ mov r10, lr
+
+/* Change PERCLK1DIV to 14 ie 14+1 */
+ ldr r0, =PCDR
+ ldr r1, =CFG_PCDR_VAL
+ str r1, [r0]
+
+/* set MCU PLL Control Register 0 */
+
+ ldr r0, =MPCTL0
+ ldr r1, =CFG_MPCTL0_VAL
+ str r1, [r0]
+
+/* set mpll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<21)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+/* set System PLL Control Register 0 */
+
+ ldr r0, =SPCTL0
+ ldr r1, =CFG_SPCTL0_VAL
+ str r1, [r0]
+
+/* set spll restart bit */
+ ldr r0, =CSCR
+ ldr r1, [r0]
+ orr r1,r1,#(1<<22)
+ str r1, [r0]
+
+ mov r2,#0x10
+1:
+ mov r3,#0x2000
+2:
+ subs r3,r3,#1
+ bne 2b
+
+ subs r2,r2,#1
+ bne 1b
+
+ ldr r0, =CSCR
+ ldr r1, =CFG_CSCR_VAL
+ str r1, [r0]
+
+/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
+ *this.....
+ *
+ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
+ * register 1, this stops it using the output of the PLL and thus runs at the
+ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
+ * use the value set in the CM_OSC registers...regardless of what you set it
+ * too! Thus, although i thought i was running at 140MHz, i'm actually running
+ * at 40!..
+
+ * Slapping this into my bootloader does the trick...
+
+ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
+ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
+ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
+ * register
+ */
+ MRC p15,0,r0,c1,c0,0
+ ORR r0,r0,#0xC0000000
+ MCR p15,0,r0,c1,c0,0
+
+ ldr r0, =GPR(0)
+ ldr r1, =CFG_GPR_A_VAL
+ str r1, [r0]
+
+ ldr r0, =GIUS(0)
+ ldr r1, =CFG_GIUS_A_VAL
+ str r1, [r0]
+
+/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
+
+ ldr r0, =FMCR
+ ldr r1, =CFG_FMCR_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0U
+ ldr r1, =CFG_CS0U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS0L
+ ldr r1, =CFG_CS0L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1U
+ ldr r1, =CFG_CS1U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS1L
+ ldr r1, =CFG_CS1L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2U
+ ldr r1, =CFG_CS2U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS2L
+ ldr r1, =CFG_CS2L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3U
+ ldr r1, =CFG_CS3U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS3L
+ ldr r1, =CFG_CS3L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4U
+ ldr r1, =CFG_CS4U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS4L
+ ldr r1, =CFG_CS4L_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5U
+ ldr r1, =CFG_CS5U_VAL
+ str r1, [r0]
+
+ ldr r0, =CS5L
+ ldr r1, =CFG_CS5L_VAL
+ str r1, [r0]
+
+/* SDRAM Setup */
+
+ ldr r0, =SDCTL0
+ ldr r1, =PRECHARGE_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08200000
+ ldr r1, =0x0 /* Issue Precharge all Command */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =AUTOREFRESH_CMD
+ str r1, [r0]
+
+ ldr r0, =0x08000000
+ ldr r1, =0x0 /* Issue AutoRefresh Command */
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0xb10a8300
+ str r1, [r0]
+
+ ldr r0, =0x08223000 /* CAS Latency 2 */
+ ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
+ str r1, [r0]
+
+ ldr r0, =SDCTL0
+ ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
+ str r1, [r0]
+
+ mov pc,r10
diff --git a/board/scb9328/scb9328.c b/board/scb9328/scb9328.c
new file mode 100644
index 0000000..a1fe0ae
--- /dev/null
+++ b/board/scb9328/scb9328.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+
+#ifdef CONFIG_SHOW_BOOT_PROGRESS
+# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
+#else
+# define SHOW_BOOT_PROGRESS(arg)
+#endif
+
+int board_init( void ){
+ DECLARE_GLOBAL_DATA_PTR;
+
+ gd->bd->bi_arch_number = 508;
+ gd->bd->bi_boot_params = 0x08000100;
+
+ return 0;
+}
+
+int dram_init( void ){
+ DECLARE_GLOBAL_DATA_PTR;
+
+#if ( CONFIG_NR_DRAM_BANKS > 0 )
+ gd->bd->bi_dram[0].start = SCB9328_SDRAM_1;
+ gd->bd->bi_dram[0].size = SCB9328_SDRAM_1_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+ gd->bd->bi_dram[1].start = SCB9328_SDRAM_2;
+ gd->bd->bi_dram[1].size = SCB9328_SDRAM_2_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 2 )
+ gd->bd->bi_dram[2].start = SCB9328_SDRAM_3;
+ gd->bd->bi_dram[2].size = SCB9328_SDRAM_3_SIZE;
+#endif
+#if ( CONFIG_NR_DRAM_BANKS > 3 )
+ gd->bd->bi_dram[3].start = SCB9328_SDRAM_4;
+ gd->bd->bi_dram[3].size = SCB9328_SDRAM_4_SIZE;
+#endif
+
+ return 0;
+}
+
+/**
+ * show_boot_progress: - indicate state of the boot process
+ *
+ * @param status: Status number - see README for details.
+ *
+ * The CSB226 does only have 3 LEDs, so we switch them on at the most
+ * important states (1, 5, 15).
+ */
+
+void show_boot_progress (int status)
+{
+ return;
+}
diff --git a/board/scb9328/u-boot.lds b/board/scb9328/u-boot.lds
new file mode 100644
index 0000000..5076303
--- /dev/null
+++ b/board/scb9328/u-boot.lds
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+ . = 0x00000000;
+
+ . = ALIGN(4);
+ .text :
+ {
+ cpu/arm920t/start.o (.text)
+ *(.text)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(.rodata) }
+
+ . = ALIGN(4);
+ .data : { *(.data) }
+
+ . = ALIGN(4);
+ .got : { *(.got) }
+
+ __u_boot_cmd_start = .;
+ .u_boot_cmd : { *(.u_boot_cmd) }
+ __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .bss : { *(.bss) }
+ _end = .;
+}
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
index 4ec7b96..1a35187 100644
--- a/board/total5200/total5200.c
+++ b/board/total5200/total5200.c
@@ -265,7 +265,7 @@
void video_get_info_str (int line_number, char *info)
{
if (line_number == 1) {
-#if CONFIG_MGT5100
+#ifdef CONFIG_MGT5100
strcpy (info, " Total5100");
#elif CONFIG_TOTAL5200_REV==1
strcpy (info, " Total5200");