mx7ulp_evk: Change APLL and its PFD0 frequencies
To support HDMI display on EVK board, the LCDIF pix clock must be
25.2Mhz. Since the its PCC divider range is from 1-8, the max rate
of LCDIF PCC source clock is 201.6Mhz. This limits the source clock
must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs
are higher than this max rate.
The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source
is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK,
NIC1 and NIC1 bus.
Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz
(25.2 * 12), with settings:
PFD0 FRAC: 32
APLL MULT: 22
APLL NUM: 2
APLL DENOM: 5
Signed-off-by: Ye Li <ye.li@nxp.com>
Tested-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
diff --git a/board/freescale/mx7ulp_evk/imximage.cfg b/board/freescale/mx7ulp_evk/imximage.cfg
index e7d87be..d4f6c3c 100644
--- a/board/freescale/mx7ulp_evk/imximage.cfg
+++ b/board/freescale/mx7ulp_evk/imximage.cfg
@@ -43,8 +43,14 @@
*/
DATA 4 0x403f00dc 0x00000000
DATA 4 0x403e0040 0x01000020
+DATA 4 0x403e0500 0x01000000
DATA 4 0x403e050c 0x80808080
-DATA 4 0x403e050c 0x8080801E
+DATA 4 0x403e0508 0x00160000
+DATA 4 0x403E0510 0x00000002
+DATA 4 0x403E0514 0x00000005
+DATA 4 0x403e0500 0x00000001
+CHECK_BITS_SET 4 0x403e0500 0x01000000
+DATA 4 0x403e050c 0x80808020
CHECK_BITS_SET 4 0x403e050c 0x00000040
DATA 4 0x403E0030 0x00000001
DATA 4 0x403e0040 0x11000020