| commit | 242b15476c94752494670a3e419e639d2df08dfd | [log] [tgz] |
|---|---|---|
| author | Michal Simek <michal.simek@xilinx.com> | Tue Sep 08 16:55:42 2015 +0200 |
| committer | Michal Simek <michal.simek@xilinx.com> | Thu Nov 19 14:03:05 2015 +0100 |
| tree | 90eb87ea90995ce5a4f302a22178381a8e2601a1 | |
| parent | e4d2318adbcff084dbbed2f84e4a51da09a1b21b [diff] |
net: zynq: Fix mdc clock division setting for 100Mbit/s Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>