| commit | 28e94bb2f7b796f58587752ab018b7d23fdc9061 | [log] [tgz] |
|---|---|---|
| author | Stefan Roese <sr@denx.de> | Fri Nov 26 15:45:22 2010 +0100 |
| committer | Stefan Roese <sr@denx.de> | Sun Nov 28 11:06:47 2010 +0100 |
| tree | d753ad2372c254ea98e9c53ddc97fbe0a429e7ea | |
| parent | 844f07d8a1f1330c97631b23fbf6425db2dc1508 [diff] |
ppc4xx/POST: Handle cached SDRAM correctly in Denali (440EPx) ECC POST This patch fixes a problem in the Denali (440EPx) SDRAM ECC POST test. When cache is enabled in the SDRAM area, the values written to SDRAM need to be flushed from cache to SDRAM using the dcfb instruction. Without this patch the POST ECC test failed. Now its working again on platforms with cache enabled in SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>