x86: ivybridge: Add early LPC init so that serial works
The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device
which provides a serial port. This is accessible on Chromebooks, so enable
it early in the boot process.
Signed-off-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index ff6b7b3..5d7640b 100644
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -11,16 +11,21 @@
*/
#include <common.h>
+#include <errno.h>
+#include <fdtdec.h>
#include <asm/cpu.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
+#include <asm/arch/pch.h>
DECLARE_GLOBAL_DATA_PTR;
int arch_cpu_init(void)
{
+ const void *blob = gd->fdt_blob;
struct pci_controller *hose;
+ int node;
int ret;
post_code(POST_CPU_INIT);
@@ -34,6 +39,13 @@
if (ret)
return ret;
+ node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+ if (node < 0)
+ return -ENOENT;
+ ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
+ if (ret)
+ return ret;
+
return 0;
}