ufs: qcom: initialise in G3/FAST_MODE
We don't yet have a nice way to get the max clk frequency (should parse
from freq-table-hz in DT), but all platforms are either 150 or 300MHz.
We can just program in the timings for 300MHz and it doesn't seem to
break SDM845 - but more testing needed.
This fixes UFS being extremely slow and buggy on SM8250 due to being
stuck at the slowest speed with misconfigured timings.
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
diff --git a/drivers/ufs/qcom-ufshcd.c b/drivers/ufs/qcom-ufshcd.c
index ca55c3e..a1f4a6a 100644
--- a/drivers/ufs/qcom-ufshcd.c
+++ b/drivers/ufs/qcom-ufshcd.c
@@ -521,16 +521,6 @@
{UFS_HS_G3, 0x92},
};
- /*
- * The Qunipro controller does not use following registers:
- * SYS1CLK_1US_REG, TX_SYMBOL_CLK_1US_REG, CLK_NS_REG &
- * UFS_REG_PA_LINK_STARTUP_TIMER
- * But UTP controller uses SYS1CLK_1US_REG register for Interrupt
- * Aggregation logic.
- */
- if (ufs_qcom_cap_qunipro(priv))
- return 0;
-
if (gear == 0) {
dev_err(hba->dev, "%s: invalid gear = %d\n", __func__, gear);
return -EINVAL;
@@ -539,12 +529,15 @@
core_clk_rate = clk_get_rate(priv->core_clk);
/* If frequency is smaller than 1MHz, set to 1MHz */
- if (core_clk_rate < DEFAULT_CLK_RATE_HZ)
+ if (core_clk_rate < DEFAULT_CLK_RATE_HZ || IS_ERR_VALUE(core_clk_rate))
core_clk_rate = DEFAULT_CLK_RATE_HZ;
+ debug("%s: core_clk_rate: %lu\n", __func__, core_clk_rate);
+
core_clk_cycles_per_us = core_clk_rate / USEC_PER_SEC;
if (ufshcd_readl(hba, REG_UFS_SYS1CLK_1US) != core_clk_cycles_per_us) {
ufshcd_writel(hba, core_clk_cycles_per_us, REG_UFS_SYS1CLK_1US);
+ ufshcd_readl(hba, REG_UFS_SYS1CLK_1US);
/*
* make sure above write gets applied before we return from
* this function.
@@ -552,9 +545,6 @@
mb();
}
- if (ufs_qcom_cap_qunipro(priv))
- return 0;
-
core_clk_period_in_ns = NSEC_PER_SEC / core_clk_rate;
core_clk_period_in_ns <<= OFFSET_CLK_NS_REG;
core_clk_period_in_ns &= MASK_CLK_NS_REG;
@@ -678,8 +668,8 @@
switch (status) {
case PRE_CHANGE:
- if (ufs_qcom_cfg_timers(hba, UFS_PWM_G1, SLOWAUTO_MODE,
- 0, true)) {
+ if (ufs_qcom_cfg_timers(hba, UFS_HS_G3, FAST_MODE,
+ PA_HS_MODE_B, true)) {
dev_err(hba->dev, "%s: ufs_qcom_cfg_timers() failed\n",
__func__);
return -EINVAL;
@@ -691,7 +681,7 @@
* divider
*/
err = ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(hba,
- 150);
+ 300);
/*
* Some UFS devices (and may be host) have issues if LCC is
diff --git a/drivers/ufs/ufs-qcom.h b/drivers/ufs/ufs-qcom.h
index be5f558..431ba1c 100644
--- a/drivers/ufs/ufs-qcom.h
+++ b/drivers/ufs/ufs-qcom.h
@@ -13,7 +13,7 @@
#define MPHY_TX_FSM_STATE 0x41
#define TX_FSM_HIBERN8 0x1
#define HBRN8_POLL_TOUT_MS 100
-#define DEFAULT_CLK_RATE_HZ 1000000
+#define DEFAULT_CLK_RATE_HZ 300000000
#define BUS_VECTOR_NAME_LEN 32
#define MAX_SUPP_MAC 64