commit 2c597855aa17d11520da642d03c82ff0c68042ab
author Samuel Holland <samuel@sholland.org> Wed Apr 27 15:31:27 2022 -0500
committer Andre Przywara <andre.przywara@arm.com> Mon May 23 00:37:51 2022 +0100
tree 626fe5d65103c387d7afeec408261e6d02814916
parent 2d648e6982e970755e78f9644bbfbe0efef43703

ARM: dts: sunxi: H2+/H3/H5: Sync from Linux v5.18-rc1

Copy the devicetree source for the H2+/H3/H5 SoCs and all existing
boards from the Linux v5.18-rc1 tag.

To maintain ABI compatibility with existing LTS kernels, one change
moving some IP blocks to the r_intc interrupt controller is excluded.
This effectively reverts Linux commits 994e5818392c and 9fdef3c3d8c2.

This commit also adds the following new board devicetree:
 - sun8i-h3-nanopi-r1.dts

This update should not impact any existing U-Boot functionality.

Signed-off-by: Samuel Holland <samuel@sholland.org>

arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi

diff --git a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
index 19b3b23..9e14fe5 100644
--- a/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
+++ b/arch/arm/dts/sunxi-libretech-all-h3-cc.dtsi
@@ -49,6 +49,7 @@
 			label = "power";
 			linux,code = <KEY_POWER>;
 			gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+			wakeup-source;
 		};
 	};
 
@@ -128,6 +129,18 @@
 	cpu-supply = <&reg_vdd_cpux>;
 };
 
+&cpu1 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu2 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
+&cpu3 {
+	cpu-supply = <&reg_vdd_cpux>;
+};
+
 &de {
 	status = "okay";
 };