Convert CONFIG_SYS_PMAN et al to Kconfig
This converts the following to Kconfig:
CONFIG_NOBQFMAN
CONFIG_SYS_DPAA_DCE
CONFIG_SYS_DPAA_FMAN
CONFIG_SYS_DPAA_PME
CONFIG_SYS_DPAA_RMAN
CONFIG_SYS_PMAN
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp
index 8c5a6f6..805fe93 100644
--- a/arch/Kconfig.nxp
+++ b/arch/Kconfig.nxp
@@ -251,3 +251,6 @@
config HAS_FSL_DR_USB
def_bool y
depends on USB_EHCI_HCD && PPC
+
+config SYS_DPAA_FMAN
+ bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ebca11d..2862257 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -69,6 +69,7 @@
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
+ select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
@@ -106,6 +107,7 @@
select GICV2
select HAS_FSL_XHCI_USB if USB_HOST
select SKIP_LOWLEVEL_INIT
+ select SYS_DPAA_FMAN
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 6440ce7..f18407b 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -24,11 +24,7 @@
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
-#if defined(CONFIG_SYS_DPAA_FMAN) || \
- defined(CONFIG_ARCH_LS1046A) || \
- defined(CONFIG_ARCH_LS1043A)
- u32 rcw_tmp;
-#endif
+ __maybe_unused u32 rcw_tmp;
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
@@ -96,7 +92,7 @@
#define HWA_CGA_M1_CLK_SEL 0xe0000000
#define HWA_CGA_M1_CLK_SHIFT 29
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
rcw_tmp = in_be32(&gur->rcwsr[7]);
switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
case 2:
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index e972603..ad20d71 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -41,7 +41,7 @@
/* setup general icid offsets */
set_icid(icid_tbl, icid_tbl_sz);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
#endif
}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
index 3bd993b..4880a31 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -59,7 +59,7 @@
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index abd847b..e47d3af 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -58,7 +58,7 @@
int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
-#ifdef CONFIG_SYS_DPAA_FMAN
+#if defined(CONFIG_SYS_DPAA_FMAN) && !defined(CONFIG_SPL_BUILD)
struct fman_icid_id_table fman_icid_tbl[] = {
/* port id, icid */
SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 24d3f1f..f236156 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -252,6 +252,8 @@
bool "Support kmcent2"
select VENDOR_KM
select FSL_CORENET
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_L3_SIZE_256KB
endchoice
@@ -618,6 +620,9 @@
select E500MC
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
+ select SYS_DPAA_RMAN
select SYS_FSL_ERRATUM_A004510
select SYS_FSL_ERRATUM_A004849
select SYS_FSL_ERRATUM_A005275
@@ -762,6 +767,7 @@
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
@@ -792,6 +798,8 @@
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -822,6 +830,8 @@
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_FMAN
+ select SYS_DPAA_PME
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
@@ -851,6 +861,10 @@
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_DCE if !NOBQFMAN
+ select SYS_DPAA_FMAN if !NOBQFMAN
+ select SYS_DPAA_PME if !NOBQFMAN
+ select SYS_DPAA_RMAN if !NOBQFMAN
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A006379
select SYS_FSL_ERRATUM_A006593
@@ -871,6 +885,7 @@
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
+ select SYS_PMAN if !NOBQFMAN
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
@@ -886,6 +901,10 @@
select FSL_CORENET
select FSL_LAW
select SYS_CACHE_SHIFT_6
+ select SYS_DPAA_DCE if !NOBQFMAN
+ select SYS_DPAA_FMAN if !NOBQFMAN
+ select SYS_DPAA_PME if !NOBQFMAN
+ select SYS_DPAA_RMAN if !NOBQFMAN
select SYS_FSL_DDR_VER_47
select SYS_FSL_ERRATUM_A004468
select SYS_FSL_ERRATUM_A005871
@@ -907,6 +926,7 @@
select SYS_FSL_SRIO_LIODN
select SYS_FSL_QMAN_V3 if SYS_DPAA_QBMAN
select SYS_FSL_USB_DUAL_PHY_ENABLE
+ select SYS_PMAN if !NOBQFMAN
select SYS_PPC64
select FSL_IFC
imply CMD_SATA
@@ -947,6 +967,9 @@
help
Enable PowerPC E6500 core
+config NOBQFMAN
+ bool
+
config FSL_LAW
bool
help
@@ -1019,6 +1042,15 @@
if changed by pre-boot regime. The value here must match
the current value in SoC. If not sure, do not change.
+config SYS_DPAA_PME
+ bool
+
+config SYS_DPAA_DCE
+ bool
+
+config SYS_DPAA_RMAN
+ bool
+
config A003399_NOR_WORKAROUND
bool
help
@@ -1195,6 +1227,9 @@
config FSL_PCIE_RESET
bool
+config SYS_PMAN
+ bool
+
config SYS_FSL_RAID_ENGINE
bool