commit 2db916e14410e3ec1738508c7bf4dfeb2b299ae7
author Peter Pearse <peter.pearse@arm.com> Thu Nov 15 08:45:13 2007 +0000
committer Peter Pearse <peter.pearse@arm.com> Thu Nov 15 08:45:13 2007 +0000
tree eaa4610ac316473776e51a96fac09c2c008824f9
parent dd28e10d9429fcc8ffb532698bda8f3ead674d96

Correction patch

board/apollon/mem.h

diff --git a/board/apollon/mem.h b/board/apollon/mem.h
index aed7e1d..5bc96fa 100644
--- a/board/apollon/mem.h
+++ b/board/apollon/mem.h
@@ -44,15 +44,15 @@
 #define APOLLON_242x_SDRC_DLLAB_CTRL_166MHz	0x00000506
 
 #ifdef PRCM_CONFIG_I
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
-# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_166MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_166MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_166MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_166MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_166MHz
 #elif PRCM_CONFIG_II
-# define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
-# define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
-# define APOLLON_2420_SDRC_RFR_CTRL		APOLLON_242X_SDRC_RFR_CTRL_100MHz
-# define APOLLON_2420_SDRC_DLLAB_CTRL		APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLA_0	APOLLON_242X_SDRC_ACTIM_CTRLA_0_100MHz
+#define APOLLON_2420_SDRC_ACTIM_CTRLB_0	APOLLON_242X_SDRC_ACTIM_CTRLB_0_100MHz
+#define APOLLON_2420_SDRC_RFR_CTRL	APOLLON_242X_SDRC_RFR_CTRL_100MHz
+#define APOLLON_2420_SDRC_DLLAB_CTRL	APOLLON_242x_SDRC_DLLAB_CTRL_100MHz
 #endif
 
 /* GPMC settings */