commit 2dea3b3e7b281f6b3b9fde318749212e02b3e0a2
author Marek Vasut <marek.vasut@gmail.com> Sat May 13 15:57:39 2017 +0200
committer Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Mon May 22 04:38:26 2017 +0900
tree c64476372b23921986988a854c5d0a9f36d149c4
parent e965c890088c9ee4b43b963530bb1805e49a6d6c

ARM: rmobile: Add R8A7796 support

Add Kconfig entry for the R8A7796 RCar M3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>

include/configs/rcar-gen3-common.h

diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h
index c87d319..304478a 100644
--- a/include/configs/rcar-gen3-common.h
+++ b/include/configs/rcar-gen3-common.h
@@ -2,7 +2,7 @@
  * include/configs/rcar-gen3-common.h
  *	This file is R-Car Gen3 common configuration file.
  *
- * Copyright (C) 2015 Renesas Electronics Corporation
+ * Copyright (C) 2015-2017 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -55,10 +55,31 @@
 #define CONFIG_SYS_TEXT_BASE		0x50000000
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_TEXT_BASE + 0x7fff0)
 
-#define CONFIG_SYS_SDRAM_BASE		(0x48000000)
-#define CONFIG_SYS_SDRAM_SIZE		(1024u * 1024 * 1024 - 0x08000000)
-#define CONFIG_SYS_LOAD_ADDR		(0x48080000)
-#define CONFIG_NR_DRAM_BANKS		1
+#define DRAM_RSV_SIZE			0x08000000
+#if defined(CONFIG_R8A7795)
+#define CONFIG_NR_DRAM_BANKS		4
+#define PHYS_SDRAM_1			(0x40000000 + DRAM_RSV_SIZE)
+#define PHYS_SDRAM_1_SIZE		(0x40000000u - DRAM_RSV_SIZE)
+#define PHYS_SDRAM_2			0x500000000
+#define PHYS_SDRAM_2_SIZE		0x40000000u
+#define PHYS_SDRAM_3			0x600000000
+#define PHYS_SDRAM_3_SIZE		0x40000000u
+#define PHYS_SDRAM_4			0x700000000
+#define PHYS_SDRAM_4_SIZE		0x40000000u
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
+#elif defined(CONFIG_R8A7796)
+#define CONFIG_NR_DRAM_BANKS		2
+#define PHYS_SDRAM_1			(0x40000000 + DRAM_RSV_SIZE)
+#define PHYS_SDRAM_1_SIZE		(0x80000000u - DRAM_RSV_SIZE)
+#define PHYS_SDRAM_2			0x0600000000
+#define PHYS_SDRAM_2_SIZE		0x80000000u
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE		PHYS_SDRAM_1_SIZE
+#endif
+#define CONFIG_SYS_LOAD_ADDR		0x48080000
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_SDRAM_SIZE
 
 #define CONFIG_SYS_MONITOR_BASE		0x00000000
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)