commit 2eba87a30a0a119b21e3a99fa9d49f041722214d
author Stephen Warren <swarren@nvidia.com> Tue Apr 22 14:37:57 2014 -0600
committer Tom Warren <twarren@nvidia.com> Tue May 13 10:41:32 2014 -0700
tree 522c2695af42d6fb4c17663ab1c595e8da4f32b8
parent 4ff213b8e478ee06feaee3505b4228163661bd3f

ARM: tegra: update Venice2 pinmux

This re-imports the entire Venice2 pinmux data from the board's master
spreadsheet, and makes use of the new IO clamping GPIO initialization
table features. This makes the board port fully compliant with the
required HW-defined pinmux initialization sequence.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

board/nvidia/venice2/venice2.c

diff --git a/board/nvidia/venice2/venice2.c b/board/nvidia/venice2/venice2.c
index 15082c4..c56ef12 100644
--- a/board/nvidia/venice2/venice2.c
+++ b/board/nvidia/venice2/venice2.c
@@ -6,12 +6,9 @@
  */
 
 #include <common.h>
-#include <asm-generic/gpio.h>
 #include <asm/arch/gpio.h>
-#include <asm/arch/gp_padctrl.h>
 #include <asm/arch/pinmux.h>
 #include "pinmux-config-venice2.h"
-#include <i2c.h>
 
 /*
  * Routine: pinmux_init
@@ -19,16 +16,14 @@
  */
 void pinmux_init(void)
 {
-	pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
-		ARRAY_SIZE(tegra124_pinmux_set_nontristate));
+	pinmux_set_tristate_input_clamping();
 
-	pinmux_config_pingrp_table(tegra124_pinmux_common,
-		ARRAY_SIZE(tegra124_pinmux_common));
+	gpio_config_table(venice2_gpio_inits,
+			  ARRAY_SIZE(venice2_gpio_inits));
 
-	pinmux_config_pingrp_table(unused_pins_lowpower,
-		ARRAY_SIZE(unused_pins_lowpower));
+	pinmux_config_pingrp_table(venice2_pingrps,
+				   ARRAY_SIZE(venice2_pingrps));
 
-	/* Initialize any non-default pad configs (APB_MISC_GP regs) */
-	pinmux_config_drvgrp_table(venice2_padctrl,
-		ARRAY_SIZE(venice2_padctrl));
+	pinmux_config_drvgrp_table(venice2_drvgrps,
+				   ARRAY_SIZE(venice2_drvgrps));
 }