PCI: zynqmp: Add ZynqMP NWL PCIe root port driver
This patch adds the PCIe controller driver for the Xilinx / AMD ZynqMP
NWL PCIe Bridge as root port. The driver source is partly copied from
the Linux PCI driver and modified to enable usage in U-Boot (e.g.
simplified and interrupt support removed).
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Pali Rohár <pali@kernel.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Michal Simek <michal.simek@amd.com>
Tested-by: Michal Simek <michal.simek@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Pali Rohár <pali@kernel.org>
Link: https://lore.kernel.org/r/20230525094918.111949-1-sr@denx.de
Signed-off-by: Michal Simek <michal.simek@amd.com>
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index ef328d2..60d98d1 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -374,4 +374,11 @@
Say Y here if you want to enable PCIe controller support on
UniPhier SoCs.
+config PCIE_XILINX_NWL
+ bool "Xilinx NWL PCIe controller"
+ depends on ARCH_ZYNQMP
+ help
+ Say 'Y' here if you want support for Xilinx / AMD NWL PCIe
+ controller as Root Port.
+
endif