net: xilinx: axi_emac: Typecast flush_cache arguments
flush_cache() arguments are not type casted to take care of 64 bit
systems. Use phys_addr_t to type cast for it to work properly for 32 bit
and 64 bit systems.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
diff --git a/drivers/net/xilinx_axi_emac.c b/drivers/net/xilinx_axi_emac.c
index c56c4d0..8af3711 100644
--- a/drivers/net/xilinx_axi_emac.c
+++ b/drivers/net/xilinx_axi_emac.c
@@ -500,11 +500,11 @@
#endif
rx_bd.cntrl = sizeof(rxframe);
/* Flush the last BD so DMA core could see the updates */
- flush_cache((u32)&rx_bd, sizeof(rx_bd));
+ flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache can contain uninitialized data */
- flush_cache((u32)&rxframe, sizeof(rxframe));
+ flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
/* Start the hardware */
temp = readl(&priv->dmarx->control);
@@ -538,7 +538,7 @@
len = PKTSIZE_ALIGN;
/* Flush packet to main memory to be trasfered by DMA */
- flush_cache((u32)ptr, len);
+ flush_cache((phys_addr_t)ptr, len);
/* Setup Tx BD */
memset(&tx_bd, 0, sizeof(tx_bd));
@@ -554,7 +554,7 @@
XAXIDMA_BD_CTRL_TXEOF_MASK;
/* Flush the last BD so DMA core could see the updates */
- flush_cache((u32)&tx_bd, sizeof(tx_bd));
+ flush_cache((phys_addr_t)&tx_bd, sizeof(tx_bd));
if (readl(&priv->dmatx->status) & XAXIDMA_HALTED_MASK) {
u32 temp;
@@ -654,11 +654,11 @@
rx_bd.cntrl = sizeof(rxframe);
/* Write bd to HW */
- flush_cache((u32)&rx_bd, sizeof(rx_bd));
+ flush_cache((phys_addr_t)&rx_bd, sizeof(rx_bd));
/* It is necessary to flush rxframe because if you don't do it
* then cache will contain previous packet */
- flush_cache((u32)&rxframe, sizeof(rxframe));
+ flush_cache((phys_addr_t)&rxframe, sizeof(rxframe));
/* Rx BD is ready - start again */
axienet_dma_write(&rx_bd, &priv->dmarx->tail);