commit 329e023868f28fd2cda31dc788017ef7c48fb1a8
author Pragnesh Patel <pragnesh.patel@sifive.com> Fri May 29 11:33:32 2020 +0530
committer Andes <uboot@andestech.com> Thu Jun 04 09:44:09 2020 +0800
tree 82ee7dbb4ca86483275286099b026e7b7bf71d73
parent 1ba43d29eb626ee813650baf12a72a31ed2bffca

riscv: sifive: dts: fu540: set ethernet clock rate

Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps,
Earlier this is done by FSBL. With this change We can remove the
ethernet clock rate code from FSBL.

Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>

arch/riscv/dts/fu540-c000-u-boot.dtsi

diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi
index fc91a7c..9bba554 100644
--- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
@@ -82,3 +82,8 @@
 &qspi2 {
 	u-boot,dm-spl;
 };
+
+&eth0 {
+	assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+	assigned-clock-rates = <125000000>;
+};